ZHCSQM7A may   2022  – march 2023 TPS65219

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1 Converter
    7. 6.7  BUCK2, BUCK3 Converter
    8. 6.8  General Purpose LDOs (LDO1, LDO2)
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 6.11 Voltage and Temperature Monitors
    12. 6.12 I2C Interface
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  Reset to SoC (nRSTOUT)
      5. 7.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 7.3.6  Linear Regulators (LDO1 through LDO4)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 7.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 7.3.12 I2C-Compatible Interface
        1. 7.3.12.1 Data Validity
        2. 7.3.12.2 Start and Stop Conditions
        3. 7.3.12.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 Fault Handling
    5. 7.5 User Registers
    6. 7.6 Device Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 8.2.3.2 LDO1, LDO2 Design Procedure
        3. 8.2.3.3 LDO3, LDO4 Design Procedure
        4. 8.2.3.4 VSYS, VDD1P8
        5. 8.2.3.5 Digital Signals Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSM|32
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)

7.6 Device Registers

Table 7-6 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.

Table 7-6 DEVICE Registers
OffsetAcronymRegister NameSection
0hTI_DEV_IDDevice IDGo
1hNVM_IDNVM configuration IDGo
2hENABLE_CTRLEnable/Push-Button/Vsense ControlGo
3hBUCKS_CONFIGGeneric Buck ConfigurationGo
4hLDO4_VOUTLDO4 ConfigurationGo
5hLDO3_VOUTLDO3 ConfigurationGo
6hLDO2_VOUTLDO2 ConfigurationGo
7hLDO1_VOUTLDO1 ConfigurationGo
8hBUCK3_VOUTBuck3 ConfigurationGo
9hBUCK2_VOUTBuck2 ConfigurationGo
AhBUCK1_VOUTBuck1 ConfigurationGo
BhLDO4_SEQUENCE_SLOTPower-up and -down slot for LDO4Go
ChLDO3_SEQUENCE_SLOTPower-up and -down slot for LDO3Go
DhLDO2_SEQUENCE_SLOTPower-up and -down slot for LDO2Go
EhLDO1_SEQUENCE_SLOTPower-up and -down slot for LDO10Go
FhBUCK3_SEQUENCE_SLOTPower-up and -down slot for Buck3Go
10hBUCK2_SEQUENCE_SLOTPower-up and -down slot for Buck2Go
11hBUCK1_SEQUENCE_SLOTPower-up and -down slot for Buck1Go
12hnRST_SEQUENCE_SLOTPower-up and -down slot for nRSTOUTGo
13hGPIO_SEQUENCE_SLOTPower-up and -down slot for GPIOGo
14hGPO2_SEQUENCE_SLOTPower-up and -down slot for GPO2Go
15hGPO1_SEQUENCE_SLOTPower-up and -down slot for GPO1Go
16hPOWER_UP_SLOT_DURATION_1Slot-duration at power-up for slot0-3Go
17hPOWER_UP_SLOT_DURATION_2Slot-duration at power-up for slot4-7Go
18hPOWER_UP_SLOT_DURATION_3Slot-duration at power-up for slot8-11Go
19hPOWER_UP_SLOT_DURATION_4Slot-duration at power-up for slot12-15Go
1AhPOWER_DOWN_SLOT_DURATION_1Slot-duration at power-down for slot0-3Go
1BhPOWER_DOWN_SLOT_DURATION_2Slot-duration at power-down for slot4-7Go
1ChPOWER_DOWN_SLOT_DURATION_3Slot-duration at power-down for slot8-11Go
1DhPOWER_DOWN_SLOT_DURATION_4Slot-duration at power-down for slot12-15Go
1EhGENERAL_CONFIGLDO-undervoltage and GPO-enableGo
1FhMFP_1_CONFIGMulti-Function pin configuration1Go
20hMFP_2_CONFIGMulti-Function pin configuration2Go
21hSTBY_1_CONFIGSTBY configuration LDOs and BucksGo
22hSTBY_2_CONFIGSTBY configuration GPIO and GPOGo
23hOC_DEGL_CONFIGOvercurrent deglitch time per railGo
24hINT_MASK_UVUndervoltage fault-maskingGo
25hMASK_CONFIGWARM-masking and mask-effectGo
26hI2C_ADDRESS_REGI2C-addressGo
27hUSER_GENERAL_NVM_STORAGE_REGUser-configurable register (NVM-backed)Go
28hMANUFACTURING_VERSilicon-revision (read-only)Go
29hMFP_CTRLI2C-control for RESET, STBY, OFFGo
2AhDISCHARGE_CONFIGDischarge configuration per railGo
2BhINT_SOURCEInterrupt sourceGo
2ChINT_LDO_3_4OC, UV, SCG for LDO3 and LDO4Go
2DhINT_LDO_1_2OC, UV, SCG for LDO1 and LDO2Go
2EhINT_BUCK_3OC, UV, SCG for Buck3Go
2FhINT_BUCK_1_2OC, UV, SCG for Buck1 and Buck2Go
30hINT_SYSTEMWARM and HOT fault flagsGo
31hINT_RVRV (residual voltage) per railGo
32hINT_TIMEOUT_RV_SDRV (residual voltage) per rail causing shut-downGo
33hINT_PBPushButton status and edge-detectionGo
34hUSER_NVM_CMD_REGDIY - user programming commandsGo
35hPOWER_UP_STATUS_REGPower-up status and STATEGo
36hSPARE_2Spare register (not NVM-backed)Go
37hSPARE_3Spare register (not NVM-backed)Go
41hFACTORY_CONFIG_2Revision of NVM-configuration (read only)Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
WSelfClrFWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1 TI_DEV_ID Register (Offset = 0h) [Reset = X]

TI_DEV_ID is shown in Figure 7-11 and described in Table 7-8.

Return to the Summary Table.

Figure 7-11 TI_DEV_ID Register
76543210
TI_DEVICE_ID
R/W-X
Table 7-8 TI_DEV_ID Register Field Descriptions
BitFieldTypeResetDescription
7-0TI_DEVICE_IDR/WX TI_DEVICE_ID[7]: 0 - TA: -40oC to 105oC, TJ: -40oC to 125oC 1 - TA: -40oC to 125oC, TJ: -40oC to 150oC TI_DEVICE_ID[6:0] = Device GPN Note: This register can be programmed only by the manufacturer! Refer to Technical Reference Manual / User's Guide for specific numbering and associated configuration. (Default from NVM memory)

7.6.2 NVM_ID Register (Offset = 1h) [Reset = X]

NVM_ID is shown in Figure 7-12 and described in Table 7-9.

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Figure 7-12 NVM_ID Register
76543210
TI_NVM_ID
R/W-X
Table 7-9 NVM_ID Register Field Descriptions
BitFieldTypeResetDescription
7-0TI_NVM_IDR/WX NVM ID of the IC Note: This register can be programmed only by the manufacturer! Refer to Technical Reference Manual / User's Guide for specific numbering and associated configuration. (Default from NVM memory)

7.6.3 ENABLE_CTRL Register (Offset = 2h) [Reset = X]

ENABLE_CTRL is shown in Figure 7-13 and described in Table 7-10.

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Figure 7-13 ENABLE_CTRL Register
76543210
RESERVEDLDO4_ENLDO3_ENLDO2_ENLDO1_ENBUCK3_ENBUCK2_ENBUCK1_EN
R-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-10 ENABLE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6LDO4_ENR/WX Enable LDO4 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
5LDO3_ENR/WX Enable LDO3 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
4LDO2_ENR/WX Enable LDO2 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
3LDO1_ENR/WX Enable LDO1 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
2BUCK3_ENR/WX Enable BUCK3 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
1BUCK2_ENR/WX Enable BUCK2 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled
0BUCK1_ENR/WX Enable BUCK1 regulator (Default from NVM memory)
0h = Disabled
1h = Enabled

7.6.4 BUCKS_CONFIG Register (Offset = 3h) [Reset = X]

BUCKS_CONFIG is shown in Figure 7-14 and described in Table 7-11.

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Figure 7-14 BUCKS_CONFIG Register
76543210
USER_NVM_SPARE_2USER_NVM_SPARE_1BUCK_SS_ENABLEBUCK_FF_ENABLEBUCK3_PHASE_CONFIGBUCK2_PHASE_CONFIG
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-11 BUCKS_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7USER_NVM_SPARE_2R/WX Spare bit in user NVM space (Default from NVM memory)
6USER_NVM_SPARE_1R/WX Spare bit in user NVM space (Default from NVM memory)
5BUCK_SS_ENABLER/WX Spread spectrum enabled on Bucks (only applicable in FF-mode) (Default from NVM memory)
0h = Spread spectrum disabled
1h = Spread spectrum enabled
4BUCK_FF_ENABLER/WX All Bucks set into fixed frequency mode NOTE: MUST NOT CHANGE AT ANY TIME! (Default from NVM memory)
0h = Quasi-fixed frequency mode
1h = Fixed frequency mode
3-2BUCK3_PHASE_CONFIGR/WX Phase of BUCK3 clock. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = 0 degrees (only applicable if Bucks are configured for fixed frequency)
1h = 90 degrees (only applicable if Bucks are configured for fixed frequency)
2h = 180 degrees (only applicable if Bucks are configured for fixed frequency)
3h = 270 degrees (only applicable if Bucks are configured for fixed frequency)
1-0BUCK2_PHASE_CONFIGR/WX Phase of BUCK2 clock. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = 0 degrees (only applicable if Bucks are configured for fixed frequency)
1h = 90 degrees (only applicable if Bucks are configured for fixed frequency)
2h = 180 degrees (only applicable if Bucks are configured for fixed frequency)
3h = 270 degrees (only applicable if Bucks are configured for fixed frequency)

7.6.5 LDO4_VOUT Register (Offset = 4h) [Reset = X]

LDO4_VOUT is shown in Figure 7-15 and described in Table 7-12.

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Figure 7-15 LDO4_VOUT Register
76543210
LDO4_SLOW_PU_RAMPLDO4_LSW_CONFIGLDO4_VSET
R/W-XR/W-XR/W-X
Table 7-12 LDO4_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7LDO4_SLOW_PU_RAMPR/WX LDO4 Power-up ramp When set high, slows down the power-up ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us. Cout max 15uF (Default from NVM memory)
0h = Fast ramp for power-up (~660us)
1h = Slow ramp for power-up (~3ms)
6LDO4_LSW_CONFIGR/WX LDO4 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = LDO Mode
1h = LSW Mode
5-0LDO4_VSETR/WX Voltage selection for LDO4. The output voltage range is from 1.2V to 3.3V. (Default from NVM memory)
0h = 1.200V
1h = 1.200V
2h = 1.200V
3h = 1.200V
4h = 1.200V
5h = 1.200V
6h = 1.200V
7h = 1.200V
8h = 1.200V
9h = 1.200V
Ah = 1.200V
Bh = 1.200V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.300V
38h = 3.300V
39h = 3.300V
3Ah = 3.300V
3Bh = 3.300V
3Ch = 3.300V
3Dh = 3.300V
3Eh = 3.300V
3Fh = 3.300V

7.6.6 LDO3_VOUT Register (Offset = 5h) [Reset = X]

LDO3_VOUT is shown in Figure 7-16 and described in Table 7-13.

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Figure 7-16 LDO3_VOUT Register
76543210
LDO3_SLOW_PU_RAMPLDO3_LSW_CONFIGLDO3_VSET
R/W-XR/W-XR/W-X
Table 7-13 LDO3_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7LDO3_SLOW_PU_RAMPR/WX LDO3 Power-up ramp When set high, slows down the power-up ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us. Cout max 15uF (Default from NVM memory)
0h = Fast ramp for power-up (~660us)
1h = Slow ramp for power-up (~3ms)
6LDO3_LSW_CONFIGR/WX LDO3 LDO or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = LDO Mode
1h = LSW Mode
5-0LDO3_VSETR/WX Voltage selection for LDO3. The output voltage range is from 1.2V to 3.3V. (Default from NVM memory)
0h = 1.200V
1h = 1.200V
2h = 1.200V
3h = 1.200V
4h = 1.200V
5h = 1.200V
6h = 1.200V
7h = 1.200V
8h = 1.200V
9h = 1.200V
Ah = 1.200V
Bh = 1.200V
Ch = 1.200V
Dh = 1.250V
Eh = 1.300V
Fh = 1.350V
10h = 1.400V
11h = 1.450V
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.300V
38h = 3.300V
39h = 3.300V
3Ah = 3.300V
3Bh = 3.300V
3Ch = 3.300V
3Dh = 3.300V
3Eh = 3.300V
3Fh = 3.300V

7.6.7 LDO2_VOUT Register (Offset = 6h) [Reset = X]

LDO2_VOUT is shown in Figure 7-17 and described in Table 7-14.

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Figure 7-17 LDO2_VOUT Register
76543210
LDO2_LSW_CONFIGLDO2_BYP_CONFIGLDO2_VSET
R/W-XR/W-XR/W-X
Table 7-14 LDO2_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7LDO2_LSW_CONFIGR/WX LDO2 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = Not Applicable (LDO2 not configured as load-switch)
1h = LDO1 configured as Load-switch
6LDO2_BYP_CONFIGR/WX LDO2 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG 0x0)
1h = LDO2 configured as Bypass (only applicable if LDO2_LSW_CONFIG 0x0)
5-0LDO2_VSETR/WX Voltage selection for LDO2. The output voltage range is from 0.6V to 3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode. (Default from NVM memory)
0h = 0.600V / n/a for bypass and LSW
1h = 0.650V / n/a for bypass and LSW
2h = 0.700V / n/a for bypass and LSW
3h = 0.750V / n/a for bypass and LSW
4h = 0.800V / n/a for bypass and LSW
5h = 0.850V / n/a for bypass and LSW
6h = 0.900V / n/a for bypass and LSW
7h = 0.950V / n/a for bypass and LSW
8h = 1.000V / n/a for bypass and LSW
9h = 1.050V / n/a for bypass and LSW
Ah = 1.100V / n/a for bypass and LSW
Bh = 1.150V / n/a for bypass and LSW
Ch = 1.200V / n/a for bypass and LSW
Dh = 1.250V / n/a for bypass and LSW
Eh = 1.300V / n/a for bypass and LSW
Fh = 1.350V / n/a for bypass and LSW
10h = 1.400V / n/a for bypass and LSW
11h = 1.450V / n/a for bypass and LSW
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.350V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
3Fh = 3.400V

7.6.8 LDO1_VOUT Register (Offset = 7h) [Reset = X]

LDO1_VOUT is shown in Figure 7-18 and described in Table 7-15.

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Figure 7-18 LDO1_VOUT Register
76543210
LDO1_LSW_CONFIGLDO1_BYP_CONFIGLDO1_VSET
R/W-XR/W-XR/W-X
Table 7-15 LDO1_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7LDO1_LSW_CONFIGR/WX LDO1 LDO/Bypass or LSW Mode. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = Not Applicable (LDO1 not configured as load-switch)
1h = LDO1 configured as Load-switch
6LDO1_BYP_CONFIGR/WX LDO1 LDO or Bypass Mode. (Default from NVM memory)
0h = LDO1 configured as LDO (only applicable if LDO1_LSW_CONFIG 0x0)
1h = LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG 0x0)
5-0LDO1_VSETR/WX Voltage selection for LDO1. The output voltage range is from 0.6V to 3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode. (Default from NVM memory)
0h = 0.600V / n/a for bypass and LSW
1h = 0.650V / n/a for bypass and LSW
2h = 0.700V / n/a for bypass and LSW
3h = 0.750V / n/a for bypass and LSW
4h = 0.800V / n/a for bypass and LSW
5h = 0.850V / n/a for bypass and LSW
6h = 0.900V / n/a for bypass and LSW
7h = 0.950V / n/a for bypass and LSW
8h = 1.000V / n/a for bypass and LSW
9h = 1.050V / n/a for bypass and LSW
Ah = 1.100V / n/a for bypass and LSW
Bh = 1.150V / n/a for bypass and LSW
Ch = 1.200V / n/a for bypass and LSW
Dh = 1.250V / n/a for bypass and LSW
Eh = 1.300V / n/a for bypass and LSW
Fh = 1.350V / n/a for bypass and LSW
10h = 1.400V / n/a for bypass and LSW
11h = 1.450V / n/a for bypass and LSW
12h = 1.500V
13h = 1.550V
14h = 1.600V
15h = 1.650V
16h = 1.700V
17h = 1.750V
18h = 1.800V
19h = 1.850V
1Ah = 1.900V
1Bh = 1.950V
1Ch = 2.000V
1Dh = 2.050V
1Eh = 2.100V
1Fh = 2.150V
20h = 2.200V
21h = 2.250V
22h = 2.300V
23h = 2.350V
24h = 2.400V
25h = 2.450V
26h = 2.500V
27h = 2.550V
28h = 2.600V
29h = 2.650V
2Ah = 2.700V
2Bh = 2.750V
2Ch = 2.800V
2Dh = 2.850V
2Eh = 2.900V
2Fh = 2.950V
30h = 3.000V
31h = 3.050V
32h = 3.100V
33h = 3.150V
34h = 3.200V
35h = 3.250V
36h = 3.300V
37h = 3.350V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
3Fh = 3.400V

7.6.9 BUCK3_VOUT Register (Offset = 8h) [Reset = X]

BUCK3_VOUT is shown in Figure 7-19 and described in Table 7-16.

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Figure 7-19 BUCK3_VOUT Register
76543210
BUCK3_BW_SELBUCK3_UV_THR_SELBUCK3_VSET
R/W-XR/W-XR/W-X
Table 7-16 BUCK3_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7BUCK3_BW_SELR/WX BUCK3 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6BUCK3_UV_THR_SELR/WX UV threshold selection for BUCK3. (Default from NVM memory)
0h = -5% UV detection level
1h = -10% UV detection level
5-0BUCK3_VSETR/WX Voltage selection for BUCK3. The output voltage range is from 0.6V to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
3Fh = 3.400V

7.6.10 BUCK2_VOUT Register (Offset = 9h) [Reset = X]

BUCK2_VOUT is shown in Figure 7-20 and described in Table 7-17.

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Figure 7-20 BUCK2_VOUT Register
76543210
BUCK2_BW_SELBUCK2_UV_THR_SELBUCK2_VSET
R/W-XR/W-XR/W-X
Table 7-17 BUCK2_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7BUCK2_BW_SELR/WX BUCK2 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6BUCK2_UV_THR_SELR/WX UV threshold selection for BUCK2. (Default from NVM memory)
0h = -5% UV detection level
1h = -10% UV detection level
5-0BUCK2_VSETR/WX Voltage selection for BUCK2. The output voltage range is from 0.6V to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
3Fh = 3.400V

7.6.11 BUCK1_VOUT Register (Offset = Ah) [Reset = X]

BUCK1_VOUT is shown in Figure 7-21 and described in Table 7-18.

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Figure 7-21 BUCK1_VOUT Register
76543210
BUCK1_BW_SELBUCK1_UV_THR_SELBUCK1_VSET
R/W-XR/W-XR/W-X
Table 7-18 BUCK1_VOUT Register Field Descriptions
BitFieldTypeResetDescription
7BUCK1_BW_SELR/WX BUCK1 Bandwidth selection. NOTE: ONLY CHANGE WHILE RAIL IS DISABLED! (Default from NVM memory)
0h = low bandwidth
1h = high bandwidth
6BUCK1_UV_THR_SELR/WX UV threshold selection for BUCK1. (Default from NVM memory)
0h = -5% UV detection level
1h = -10% UV detection level
5-0BUCK1_VSETR/WX Voltage selection for BUCK1. The output voltage range is from 0.6V to 3.4V. (Default from NVM memory)
0h = 0.600V
1h = 0.625V
2h = 0.650V
3h = 0.675V
4h = 0.700V
5h = 0.725V
6h = 0.750V
7h = 0.775V
8h = 0.800V
9h = 0.825V
Ah = 0.850V
Bh = 0.875V
Ch = 0.900V
Dh = 0.925V
Eh = 0.950V
Fh = 0.975V
10h = 1.000V
11h = 1.025V
12h = 1.050V
13h = 1.075V
14h = 1.100V
15h = 1.125V
16h = 1.150V
17h = 1.175V
18h = 1.200V
19h = 1.225V
1Ah = 1.250V
1Bh = 1.275V
1Ch = 1.300V
1Dh = 1.325V
1Eh = 1.350V
1Fh = 1.375V
20h = 1.400V
21h = 1.500V
22h = 1.600V
23h = 1.700V
24h = 1.800V
25h = 1.900V
26h = 2.000V
27h = 2.100V
28h = 2.200V
29h = 2.300V
2Ah = 2.400V
2Bh = 2.500V
2Ch = 2.600V
2Dh = 2.700V
2Eh = 2.800V
2Fh = 2.900V
30h = 3.000V
31h = 3.100V
32h = 3.200V
33h = 3.300V
34h = 3.400V
35h = 3.400V
36h = 3.400V
37h = 3.400V
38h = 3.400V
39h = 3.400V
3Ah = 3.400V
3Bh = 3.400V
3Ch = 3.400V
3Dh = 3.400V
3Eh = 3.400V
3Fh = 3.400V

7.6.12 LDO4_SEQUENCE_SLOT Register (Offset = Bh) [Reset = X]

LDO4_SEQUENCE_SLOT is shown in Figure 7-22 and described in Table 7-19.

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Figure 7-22 LDO4_SEQUENCE_SLOT Register
76543210
LDO4_SEQUENCE_ON_SLOTLDO4_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-19 LDO4_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4LDO4_SEQUENCE_ON_SLOTR/WX LDO4 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0LDO4_SEQUENCE_OFF_SLOTR/WX LDO4 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.13 LDO3_SEQUENCE_SLOT Register (Offset = Ch) [Reset = X]

LDO3_SEQUENCE_SLOT is shown in Figure 7-23 and described in Table 7-20.

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Figure 7-23 LDO3_SEQUENCE_SLOT Register
76543210
LDO3_SEQUENCE_ON_SLOTLDO3_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-20 LDO3_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4LDO3_SEQUENCE_ON_SLOTR/WX LDO3 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0LDO3_SEQUENCE_OFF_SLOTR/WX LDO3 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.14 LDO2_SEQUENCE_SLOT Register (Offset = Dh) [Reset = X]

LDO2_SEQUENCE_SLOT is shown in Figure 7-24 and described in Table 7-21.

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Figure 7-24 LDO2_SEQUENCE_SLOT Register
76543210
LDO2_SEQUENCE_ON_SLOTLDO2_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-21 LDO2_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4LDO2_SEQUENCE_ON_SLOTR/WX LDO2 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0LDO2_SEQUENCE_OFF_SLOTR/WX LDO2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.15 LDO1_SEQUENCE_SLOT Register (Offset = Eh) [Reset = X]

LDO1_SEQUENCE_SLOT is shown in Figure 7-25 and described in Table 7-22.

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Figure 7-25 LDO1_SEQUENCE_SLOT Register
76543210
LDO1_SEQUENCE_ON_SLOTLDO1_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-22 LDO1_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4LDO1_SEQUENCE_ON_SLOTR/WX LDO1 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0LDO1_SEQUENCE_OFF_SLOTR/WX LDO1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.16 BUCK3_SEQUENCE_SLOT Register (Offset = Fh) [Reset = X]

BUCK3_SEQUENCE_SLOT is shown in Figure 7-26 and described in Table 7-23.

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Figure 7-26 BUCK3_SEQUENCE_SLOT Register
76543210
BUCK3_SEQUENCE_ON_SLOTBUCK3_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-23 BUCK3_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4BUCK3_SEQUENCE_ON_SLOTR/WX BUCK3 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0BUCK3_SEQUENCE_OFF_SLOTR/WX BUCK3 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.17 BUCK2_SEQUENCE_SLOT Register (Offset = 10h) [Reset = X]

BUCK2_SEQUENCE_SLOT is shown in Figure 7-27 and described in Table 7-24.

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Figure 7-27 BUCK2_SEQUENCE_SLOT Register
76543210
BUCK2_SEQUENCE_ON_SLOTBUCK2_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-24 BUCK2_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4BUCK2_SEQUENCE_ON_SLOTR/WX BUCK2 Slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0BUCK2_SEQUENCE_OFF_SLOTR/WX BUCK2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.18 BUCK1_SEQUENCE_SLOT Register (Offset = 11h) [Reset = X]

BUCK1_SEQUENCE_SLOT is shown in Figure 7-28 and described in Table 7-25.

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Figure 7-28 BUCK1_SEQUENCE_SLOT Register
76543210
BUCK1_SEQUENCE_ON_SLOTBUCK1_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-25 BUCK1_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4BUCK1_SEQUENCE_ON_SLOTR/WX BUCK1 Slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0BUCK1_SEQUENCE_OFF_SLOTR/WX BUCK1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.19 nRST_SEQUENCE_SLOT Register (Offset = 12h) [Reset = X]

nRST_SEQUENCE_SLOT is shown in Figure 7-29 and described in Table 7-26.

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Figure 7-29 nRST_SEQUENCE_SLOT Register
76543210
nRST_SEQUENCE_ON_SLOTnRST_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-26 nRST_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4nRST_SEQUENCE_ON_SLOTR/WX nRST slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0nRST_SEQUENCE_OFF_SLOTR/WX nRST slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.20 GPIO_SEQUENCE_SLOT Register (Offset = 13h) [Reset = X]

GPIO_SEQUENCE_SLOT is shown in Figure 7-30 and described in Table 7-27.

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Figure 7-30 GPIO_SEQUENCE_SLOT Register
76543210
GPIO_SEQUENCE_ON_SLOTGPIO_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-27 GPIO_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4GPIO_SEQUENCE_ON_SLOTR/WX GPIO slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0GPIO_SEQUENCE_OFF_SLOTR/WX GPIO slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.21 GPO2_SEQUENCE_SLOT Register (Offset = 14h) [Reset = X]

GPO2_SEQUENCE_SLOT is shown in Figure 7-31 and described in Table 7-28.

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Figure 7-31 GPO2_SEQUENCE_SLOT Register
76543210
GPO2_SEQUENCE_ON_SLOTGPO2_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-28 GPO2_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO2_SEQUENCE_ON_SLOTR/WX GPO2 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0GPO2_SEQUENCE_OFF_SLOTR/WX GPO2 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.22 GPO1_SEQUENCE_SLOT Register (Offset = 15h) [Reset = X]

GPO1_SEQUENCE_SLOT is shown in Figure 7-32 and described in Table 7-29.

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Figure 7-32 GPO1_SEQUENCE_SLOT Register
76543210
GPO1_SEQUENCE_ON_SLOTGPO1_SEQUENCE_OFF_SLOT
R/W-XR/W-X
Table 7-29 GPO1_SEQUENCE_SLOT Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO1_SEQUENCE_ON_SLOTR/WX GPO1 slot number for power-up (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15
3-0GPO1_SEQUENCE_OFF_SLOTR/WX GPO1 slot number for power-down (Default from NVM memory)
0h = slot 0
1h = slot 1
2h = slot 2
3h = slot 3
4h = slot 4
5h = slot 5
6h = slot 6
7h = slot 7
8h = slot 8
9h = slot 9
Ah = slot 10
Bh = slot 11
Ch = slot 12
Dh = slot 13
Eh = slot 14
Fh = slot 15

7.6.23 POWER_UP_SLOT_DURATION_1 Register (Offset = 16h) [Reset = X]

POWER_UP_SLOT_DURATION_1 is shown in Figure 7-33 and described in Table 7-30.

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Figure 7-33 POWER_UP_SLOT_DURATION_1 Register
76543210
POWER_UP_SLOT_0_DURATIONPOWER_UP_SLOT_1_DURATIONPOWER_UP_SLOT_2_DURATIONPOWER_UP_SLOT_3_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-30 POWER_UP_SLOT_DURATION_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_UP_SLOT_0_DURATIONR/WX Duration of slot 0 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_UP_SLOT_1_DURATIONR/WX Duration of slot 1 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_UP_SLOT_2_DURATIONR/WX Duration of slot 2 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_UP_SLOT_3_DURATIONR/WX Duration of slot 3 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.24 POWER_UP_SLOT_DURATION_2 Register (Offset = 17h) [Reset = X]

POWER_UP_SLOT_DURATION_2 is shown in Figure 7-34 and described in Table 7-31.

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Figure 7-34 POWER_UP_SLOT_DURATION_2 Register
76543210
POWER_UP_SLOT_4_DURATIONPOWER_UP_SLOT_5_DURATIONPOWER_UP_SLOT_6_DURATIONPOWER_UP_SLOT_7_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-31 POWER_UP_SLOT_DURATION_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_UP_SLOT_4_DURATIONR/WX Duration of slot 4 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_UP_SLOT_5_DURATIONR/WX Duration of slot 5 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_UP_SLOT_6_DURATIONR/WX Duration of slot 6 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_UP_SLOT_7_DURATIONR/WX Duration of slot 7 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.25 POWER_UP_SLOT_DURATION_3 Register (Offset = 18h) [Reset = X]

POWER_UP_SLOT_DURATION_3 is shown in Figure 7-35 and described in Table 7-32.

Return to the Summary Table.

Figure 7-35 POWER_UP_SLOT_DURATION_3 Register
76543210
POWER_UP_SLOT_8_DURATIONPOWER_UP_SLOT_9_DURATIONPOWER_UP_SLOT_10_DURATIONPOWER_UP_SLOT_11_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-32 POWER_UP_SLOT_DURATION_3 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_UP_SLOT_8_DURATIONR/WX Duration of slot 8 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_UP_SLOT_9_DURATIONR/WX Duration of slot 9 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_UP_SLOT_10_DURATIONR/WX Duration of slot 10 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_UP_SLOT_11_DURATIONR/WX Duration of slot 11 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.26 POWER_UP_SLOT_DURATION_4 Register (Offset = 19h) [Reset = X]

POWER_UP_SLOT_DURATION_4 is shown in Figure 7-36 and described in Table 7-33.

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Figure 7-36 POWER_UP_SLOT_DURATION_4 Register
76543210
POWER_UP_SLOT_12_DURATIONPOWER_UP_SLOT_13_DURATIONPOWER_UP_SLOT_14_DURATIONPOWER_UP_SLOT_15_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-33 POWER_UP_SLOT_DURATION_4 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_UP_SLOT_12_DURATIONR/WX Duration of slot 12 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_UP_SLOT_13_DURATIONR/WX Duration of slot 13 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_UP_SLOT_14_DURATIONR/WX Duration of slot 14 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_UP_SLOT_15_DURATIONR/WX Duration of slot 15 during the power-up and standby-to-active sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.27 POWER_DOWN_SLOT_DURATION_1 Register (Offset = 1Ah) [Reset = X]

POWER_DOWN_SLOT_DURATION_1 is shown in Figure 7-37 and described in Table 7-34.

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Figure 7-37 POWER_DOWN_SLOT_DURATION_1 Register
76543210
POWER_DOWN_SLOT_0_DURATIONPOWER_DOWN_SLOT_1_DURATIONPOWER_DOWN_SLOT_2_DURATIONPOWER_DOWN_SLOT_3_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-34 POWER_DOWN_SLOT_DURATION_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_DOWN_SLOT_0_DURATIONR/WX Duration of slot 0 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_DOWN_SLOT_1_DURATIONR/WX Duration of slot 1 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_DOWN_SLOT_2_DURATIONR/WX Duration of slot 2 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_DOWN_SLOT_3_DURATIONR/WX Duration of slot 3 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.28 POWER_DOWN_SLOT_DURATION_2 Register (Offset = 1Bh) [Reset = X]

POWER_DOWN_SLOT_DURATION_2 is shown in Figure 7-38 and described in Table 7-35.

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Figure 7-38 POWER_DOWN_SLOT_DURATION_2 Register
76543210
POWER_DOWN_SLOT_4_DURATIONPOWER_DOWN_SLOT_5_DURATIONPOWER_DOWN_SLOT_6_DURATIONPOWER_DOWN_SLOT_7_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-35 POWER_DOWN_SLOT_DURATION_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_DOWN_SLOT_4_DURATIONR/WX Duration of slot 4 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_DOWN_SLOT_5_DURATIONR/WX Duration of slot 5 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_DOWN_SLOT_6_DURATIONR/WX Duration of slot 6 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_DOWN_SLOT_7_DURATIONR/WX Duration of slot 7 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.29 POWER_DOWN_SLOT_DURATION_3 Register (Offset = 1Ch) [Reset = X]

POWER_DOWN_SLOT_DURATION_3 is shown in Figure 7-39 and described in Table 7-36.

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Figure 7-39 POWER_DOWN_SLOT_DURATION_3 Register
76543210
POWER_DOWN_SLOT_8_DURATIONPOWER_DOWN_SLOT_9_DURATIONPOWER_DOWN_SLOT_10_DURATIONPOWER_DOWN_SLOT_11_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-36 POWER_DOWN_SLOT_DURATION_3 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_DOWN_SLOT_8_DURATIONR/WX Duration of slot 8 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_DOWN_SLOT_9_DURATIONR/WX Duration of slot 9 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_DOWN_SLOT_10_DURATIONR/WX Duration of slot 10 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_DOWN_SLOT_11_DURATIONR/WX Duration of slot 11 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.30 POWER_DOWN_SLOT_DURATION_4 Register (Offset = 1Dh) [Reset = X]

POWER_DOWN_SLOT_DURATION_4 is shown in Figure 7-40 and described in Table 7-37.

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Figure 7-40 POWER_DOWN_SLOT_DURATION_4 Register
76543210
POWER_DOWN_SLOT_12_DURATIONPOWER_DOWN_SLOT_13_DURATIONPOWER_DOWN_SLOT_14_DURATIONPOWER_DOWN_SLOT_15_DURATION
R/W-XR/W-XR/W-XR/W-X
Table 7-37 POWER_DOWN_SLOT_DURATION_4 Register Field Descriptions
BitFieldTypeResetDescription
7-6POWER_DOWN_SLOT_12_DURATIONR/WX Duration of slot 12 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
5-4POWER_DOWN_SLOT_13_DURATIONR/WX Duration of slot 13 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
3-2POWER_DOWN_SLOT_14_DURATIONR/WX Duration of slot 14 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms
1-0POWER_DOWN_SLOT_15_DURATIONR/WX Duration of slot 15 during the power-down and active-to-standby sequences. (Default from NVM memory)
0h = 0ms
1h = 1.5ms
2h = 3ms
3h = 10ms

7.6.31 GENERAL_CONFIG Register (Offset = 1Eh) [Reset = X]

GENERAL_CONFIG is shown in Figure 7-41 and described in Table 7-38.

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Figure 7-41 GENERAL_CONFIG Register
76543210
BYPASS_RAILS_DISCHARGED_CHECKLDO4_UV_THRLDO3_UV_THRLDO2_UV_THRLDO1_UV_THRGPIO_ENGPO2_ENGPO1_EN
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-38 GENERAL_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7BYPASS_RAILS_DISCHARGED_CHECKR/WX Bypass the all-rails discharged check to commence a transition to ACTIVE state, and the rails-in-slot discharged check executed in each slot during a power-down to INITIALIZE state. Does not bypass the check for RV(Pre-biased) condition prior to enabling a regulator. (Default from NVM memory)
0h = Discharged checks enforced
1h = Discharged checks during PowerUp and PowerDown bypassed
6LDO4_UV_THRR/WX UV threshold selection bit for LDO4. (Default from NVM memory)
0h = -5% UV detection level (only applicable if configured as LDO)
1h = -10% UV detection level (only applicable if configured as LDO)
5LDO3_UV_THRR/WX UV threshold selection bit for LDO3. (Default from NVM memory)
0h = -5% UV detection level (only applicable if configured as LDO)
1h = -10% UV detection level (only applicable if configured as LDO)
4LDO2_UV_THRR/WX UV threshold selection bit for LDO2. (Default from NVM memory)
0h = -5% UV detection level (only applicable if configured as LDO)
1h = -10% UV detection level (only applicable if configured as LDO)
3LDO1_UV_THRR/WX UV threshold selection bit for LDO1. (Default from NVM memory)
0h = -5% UV detection level (only applicable if configured as LDO)
1h = -10% UV detection level (only applicable if configured as LDO)
2GPIO_ENR/WX Both an enable and state control of GPIO. This bit enables the GPIO function and also controls the state of the GPIO pin. (Default from NVM memory)
0h = The GPIO function is disabled. The output state is low.
1h = The GPIO function is enabled. The output state is 'high'.
1GPO2_ENR/WX Both an enable and state control of GPO2. This bit enables the GPO2 function and also controls the state of the GPO2 pin. (Default from NVM memory)
0h = The GPO2 function is disabled. The output state is low.
1h = The GPO2 function is enabled. The output state is Hi-Z.
0GPO1_ENR/WX Both an enable and state control of GPO1. This bit enables the GPO1 function and also controls the state of the GPO1 pin. (Default from NVM memory)
0h = The GPO1 function is disabled. The output state is low.
1h = The GPO1 function is enabled. The output state is Hi-Z.

7.6.32 MFP_1_CONFIG Register (Offset = 1Fh) [Reset = X]

MFP_1_CONFIG is shown in Figure 7-42 and described in Table 7-39.

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Figure 7-42 MFP_1_CONFIG Register
76543210
MODE_I2C_CTRLVSEL_SD_I2C_CTRLMODE_RESET_POLARITYMODE_STBY_POLARITYMULTI_DEVICE_ENABLEVSEL_RAILVSEL_SD_POLARITYVSEL_DDR_SD
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-39 MFP_1_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7MODE_I2C_CTRLR/WX MODE control using I2C. Consolidated with MODE control via MODE/RESET and/or MODE/STBY pins. Refer to table in the data sheet. (Default from NVM memory)
0h = Auto PFM
1h = Forced PWM
6VSEL_SD_I2C_CTRLR/WX VSEL_SD control using I2C. Applicable only if VSEL_SD/VSEL_DDR pin is configured as "VSEL_DDR". (Default from NVM memory)
0h = 1.8V
1h = LDOx_VOUT register setting
5MODE_RESET_POLARITYR/WX MODE_RESET Pin Polarity configuration. Note: Ok to change during operation, but consider immediate reaction: MODE-change or RESET-entry! (Default from NVM memory)
0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced PWM. [if configured as RESET] LOW - reset / HIGH - normal operation.
1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced PWM. [if configured as RESET] HIGH - reset / LOW - normal operation.
4MODE_STBY_POLARITYR/WX MODE_STBY Pin Polarity configuration. Note: Ok to change during operation, but consider immediate reaction: MODE-change or STATE-change! (Default from NVM memory)
0h = [if configured as MODE] LOW - auto-PFM / HIGH - forced PWM. [if configured as a STBY] LOW - STBY state / HIGH - ACTIVE state.
1h = [if configured as MODE] HIGH - auto-PFM / LOW - forced PWM. [if configured as a STBY] HIGH - STBY state / LOW - ACTIVE state.
3MULTI_DEVICE_ENABLER/WX Configures the device as a single device where GPO is used as GPO function, or as a multi-device configuration where GPO is used for synchronization with other devices. NOTE: ONLY CHANGE IN INITIALIZE STATE! (Default from NVM memory)
0h = Single-device configuration, GPIO pin configured as GPO
1h = Multi-device configuration, GPIO pin configured as GPIO
2VSEL_RAILR/WX LDO controlled by VSEL_SD/VSEL_DDR. NOTE: ONLY CHANGE IN INITIALIZE STATE! (Default from NVM memory)
0h = LDO1
1h = LDO2
1VSEL_SD_POLARITYR/WX SD Card Voltage Select Note: Ok to change during operation, but consider immediate reaction: change of SD-card supply voltage! (Default from NVM memory)
0h = LOW - 1.8V / HIGH - LDOx_VOUT register setting
1h = HIGH - 1.8V / LOW - LDOx_VOUT register setting
0VSEL_DDR_SDR/WX VSEL_SD/VSEL_DDR Configuration NOTE: ONLY CHANGE IN INITIALIZE STATE! (Default from NVM memory)
0h = VSEL pin configured as DDR to set the voltage on Buck3
1h = VSEL pin configured as SD to set the voltage on the VSEL_RAIL

7.6.33 MFP_2_CONFIG Register (Offset = 20h) [Reset = X]

MFP_2_CONFIG is shown in Figure 7-43 and described in Table 7-40.

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Figure 7-43 MFP_2_CONFIG Register
76543210
PU_ON_FSDWARM_COLD_RESET_CONFIGEN_PB_VSENSE_CONFIGEN_PB_VSENSE_DEGLMODE_RESET_CONFIGMODE_STBY_CONFIG
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-40 MFP_2_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7PU_ON_FSDR/WX Power up upon First Supply Detected (FSD). So when VSYS is applied, device does power up to ACTIVE state even if EN/PB/VSENSE pin is at OFF_REQ status. (Default from NVM memory)
0h = First Supply Detection (FSD) Disabled.
1h = First Supply Detection (FSD) Enabled.
6WARM_COLD_RESET_CONFIGR/WX Selection between WARM or COLD Reset, when a RESET event is triggered via MODE/RESET pin (does not apply to RESET via I2C) (Default from NVM memory)
0h = COLD RESET
1h = WARM RESET
5-4EN_PB_VSENSE_CONFIGR/WX Enable / Push-Button / VSENSE Configuration. Do not change via I2C after NVM load (except as a precursor before programming NVM) (Default from NVM memory)
0h = Device Enable Configuration
1h = Push Button Configuration
2h = VSENSE Configuration
3h = Device Enable Configuration
3EN_PB_VSENSE_DEGLR/WX Enable / Push-Button / VSENSE Deglitch NOTE: ONLY CHANGE IN INITIALIZE STATE! Consider immediate reaction when changing from EN/VSENSE to PB or vice versa: power-up! (Default from NVM memory)
0h = short (typ: 200ms if configured as PB)
1h = long (typ: 50ms if configured as EN or VSENSE)
2MODE_RESET_CONFIGR/WX MODE/RESET Configuration (Default from NVM memory)
0h = MODE
1h = RESET
1-0MODE_STBY_CONFIGR/WX MODE_STDBY Configuration (Default from NVM memory)
0h = MODE
1h = STBY
2h = MODE and STBY
3h = MODE

7.6.34 STBY_1_CONFIG Register (Offset = 21h) [Reset = X]

STBY_1_CONFIG is shown in Figure 7-44 and described in Table 7-41.

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Figure 7-44 STBY_1_CONFIG Register
76543210
RESERVEDLDO4_STBY_ENLDO3_STBY_ENLDO2_STBY_ENLDO1_STBY_ENBUCK3_STBY_ENBUCK2_STBY_ENBUCK1_STBY_EN
R-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-41 STBY_1_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6LDO4_STBY_ENR/WX Enable LDO4 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
5LDO3_STBY_ENR/WX Enable LDO3 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
4LDO2_STBY_ENR/WX Enable LDO2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
3LDO1_STBY_ENR/WX Enable LDO1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
2BUCK3_STBY_ENR/WX Enable BUCK3 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
1BUCK2_STBY_ENR/WX Enable BUCK2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
0BUCK1_STBY_ENR/WX Enable BUCK1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode

7.6.35 STBY_2_CONFIG Register (Offset = 22h) [Reset = X]

STBY_2_CONFIG is shown in Figure 7-45 and described in Table 7-42.

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Figure 7-45 STBY_2_CONFIG Register
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO_STBY_ENGPO2_STBY_ENGPO1_STBY_EN
R-XR-XR-XR-XR-XR/W-XR/W-XR/W-X
Table 7-42 STBY_2_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5RESERVEDRX Reserved
4RESERVEDRX Reserved
3RESERVEDRX Reserved
2GPIO_STBY_ENR/WX Enable GPIO in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
1GPO2_STBY_ENR/WX Enable GPO2 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode
0GPO1_STBY_ENR/WX Enable GPO1 in STANDBY state. (Default from NVM memory)
0h = Disabled in STBY Mode
1h = Enabled in STBY Mode

7.6.36 OC_DEGL_CONFIG Register (Offset = 23h) [Reset = X]

OC_DEGL_CONFIG is shown in Figure 7-46 and described in Table 7-43.

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Figure 7-46 OC_DEGL_CONFIG Register
76543210
RESERVEDEN_LONG_DEGL_FOR_OC_LDO4EN_LONG_DEGL_FOR_OC_LDO3EN_LONG_DEGL_FOR_OC_LDO2EN_LONG_DEGL_FOR_OC_LDO1EN_LONG_DEGL_FOR_OC_BUCK3EN_LONG_DEGL_FOR_OC_BUCK2EN_LONG_DEGL_FOR_OC_BUCK1
R-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-43 OC_DEGL_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6EN_LONG_DEGL_FOR_OC_LDO4R/WX When set, enables the long-deglitch option for OverCurrent signal of LDO4. When clear, enables the short-deglitch option for OverCurrent signal of LDO4. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO4 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO4 is ~2ms
5EN_LONG_DEGL_FOR_OC_LDO3R/WX When set, enables the long-deglitch option for OverCurrent signal of LDO3. When clear, enables the short-deglitch option for OverCurrent signal of LDO3. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO3 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO3 is ~2ms
4EN_LONG_DEGL_FOR_OC_LDO2R/WX When set, enables the long-deglitch option for OverCurrent signal of LDO2. When clear, enables the short-deglitch option for OverCurrent signal of LDO2. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO2 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO2 is ~2ms
3EN_LONG_DEGL_FOR_OC_LDO1R/WX When set, enables the long-deglitch option for OverCurrent signal of LDO1. When clear, enables the short-deglitch option for OverCurrent signal of LDO1. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals of LDO1 is ~20us
1h = Deglitch duration for OverCurrent signals of LDO1 is ~2ms
2EN_LONG_DEGL_FOR_OC_BUCK3R/WX When set, enables the long-deglitch option for OverCurrent signals of BUCK3. When clear, enables the short-deglitch option for OverCurrent signals of BUCK3. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms
1EN_LONG_DEGL_FOR_OC_BUCK2R/WX When set, enables the long-deglitch option for OverCurrent signals of BUCK2. When clear, enables the short-deglitch option for OverCurrent signals of BUCK2. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms
0EN_LONG_DEGL_FOR_OC_BUCK1R/WX When set, enables the long-deglitch option for OverCurrent signals of BUCK1. When clear, enables the short-deglitch option for OverCurrent signals of BUCK1. (Default from NVM memory)
0h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
1h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~2ms

7.6.37 INT_MASK_UV Register (Offset = 24h) [Reset = X]

INT_MASK_UV is shown in Figure 7-47 and described in Table 7-44.

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Figure 7-47 INT_MASK_UV Register
76543210
MASK_RETRY_COUNTBUCK3_UV_MASKBUCK2_UV_MASKBUCK1_UV_MASKLDO4_UV_MASKLDO3_UV_MASKLDO2_UV_MASKLDO1_UV_MASK
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-44 INT_MASK_UV Register Field Descriptions
BitFieldTypeResetDescription
7MASK_RETRY_COUNTR/WX When set, device can power up even after two retries. (Default from NVM memory)
0h = Device does retry up to 2 times, then stay off
1h = Device does retry infinitely
6BUCK3_UV_MASKR/WX BUCK3 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
5BUCK2_UV_MASKR/WX BUCK2 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
4BUCK1_UV_MASKR/WX BUCK1 Undervoltage Mask. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
3LDO4_UV_MASKR/WX LDO4 Undervoltage Mask - Always masked in BYP or LSW modes. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
2LDO3_UV_MASKR/WX LDO3 Undervoltage Mask - Always masked in BYP or LSW modes. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
1LDO2_UV_MASKR/WX LDO2 Undervoltage Mask - Always masked in BYP or LSW modes. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
0LDO1_UV_MASKR/WX LDO1 Undervoltage Mask - Always masked in BYP or LSW modes. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)

7.6.38 MASK_CONFIG Register (Offset = 25h) [Reset = X]

MASK_CONFIG is shown in Figure 7-48 and described in Table 7-45.

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Figure 7-48 MASK_CONFIG Register
76543210
MASK_INT_FOR_PBMASK_EFFECTMASK_INT_FOR_RVSENSOR_0_WARM_MASKSENSOR_1_WARM_MASKSENSOR_2_WARM_MASKSENSOR_3_WARM_MASK
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-45 MASK_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7MASK_INT_FOR_PBR/WX Masking bit to control whether nINT pin is sensitive to PushButton (PB) press/release events or not. (Default from NVM memory)
0h = un-masked (nINT pulled low for any PB events)
1h = masked (nINT not sensitive to any PB events)
6-5MASK_EFFECTR/WX Effect of masking (global) (Default from NVM memory)
0h = no state change, no nINT reaction, no bit set for Faults
1h = no state change, no nINT reaction, bit set for Faults
2h = no state change, nINT reaction, bit set for Faults (same as 11b)
3h = no state change, nINT reaction, bit set for Faults (same as 10b)
4MASK_INT_FOR_RVR/WX Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) events or not. (Default from NVM memory)
0h = un-masked (nINT pulled low for any RV events during transition to ACTIVE state or during enabling of rails)
1h = masked (nINT not sensitive to any RV events)
3SENSOR_0_WARM_MASKR/WX Die Temperature Warm Fault Mask, Sensor 0. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
2SENSOR_1_WARM_MASKR/WX Die Temperature Warm Fault Mask, Sensor 1. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
1SENSOR_2_WARM_MASKR/WX Die Temperature Warm Fault Mask, Sensor 2. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)
0SENSOR_3_WARM_MASKR/WX Die Temperature Warm Fault Mask, Sensor 3. (Default from NVM memory)
0h = un-masked (Faults reported)
1h = masked (Faults not reported)

7.6.39 I2C_ADDRESS_REG Register (Offset = 26h) [Reset = X]

I2C_ADDRESS_REG is shown in Figure 7-49 and described in Table 7-46.

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Figure 7-49 I2C_ADDRESS_REG Register
76543210
DIY_NVM_PROGRAM_CMD_ISSUEDI2C_ADDRESS
R/W-XR/W-X
Table 7-46 I2C_ADDRESS_REG Register Field Descriptions
BitFieldTypeResetDescription
7DIY_NVM_PROGRAM_CMD_ISSUEDR/WX Bit that indicates whether a DIY program command was attempted. Once set, remains always set. (Default from NVM memory)
0h = NVM data not changed
1h = NVM data attempted to be changed via DIY program command
6-0I2C_ADDRESSR/WX I2C secondary address. Note: Ok to change during operation, but consider immediate reaction: new address for read/write! (Default from NVM memory)

7.6.40 USER_GENERAL_NVM_STORAGE_REG Register (Offset = 27h) [Reset = X]

USER_GENERAL_NVM_STORAGE_REG is shown in Figure 7-50 and described in Table 7-47.

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Figure 7-50 USER_GENERAL_NVM_STORAGE_REG Register
76543210
USER_GENERAL_NVM_STORAGE
R/W-X
Table 7-47 USER_GENERAL_NVM_STORAGE_REG Register Field Descriptions
BitFieldTypeResetDescription
7-0USER_GENERAL_NVM_STORAGER/WX 8-bit NVM-based register available to the user to use to store user-data, for example NVM-ID of customer-modified NVM-version or other purposes. (Default from NVM memory)

7.6.41 MANUFACTURING_VER Register (Offset = 28h) [Reset = 00h]

MANUFACTURING_VER is shown in Figure 7-51 and described in Table 7-48.

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Figure 7-51 MANUFACTURING_VER Register
76543210
SILICON_REV
R-0h
Table 7-48 MANUFACTURING_VER Register Field Descriptions
BitFieldTypeResetDescription
7-0SILICON_REVR0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal Silicon Revision - Hard wired (not under NVM control)

7.6.42 MFP_CTRL Register (Offset = 29h) [Reset = X]

MFP_CTRL is shown in Figure 7-52 and described in Table 7-49.

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Figure 7-52 MFP_CTRL Register
76543210
RESERVEDRESERVEDRESERVEDGPIO_STATUSWARM_RESET_I2C_CTRLCOLD_RESET_I2C_CTRLSTBY_I2C_CTRLI2C_OFF_REQ
R-XR-XR-XR-0hR/WSelfClrF-0hR/W-0hR/W-0hR/WSelfClrF-0h
Table 7-49 MFP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5RESERVEDRX Reserved
4GPIO_STATUSR0h Indicates the real-time value of GPIO pin
0h = The GPIO pin is currently '0'
1h = The GPIO pin is currently '1'
3WARM_RESET_I2C_CTRLR/WSelfClrF0h Triggers a WARM RESET when written as '1'. Note: This bit self-clears automatically, so cannot be read as '1' after the write.
0h = normal operation
1h = WARM_RESET
2COLD_RESET_I2C_CTRLR/W0h Triggers a COLD RESET when set high. Cleared upon entry to INITIALIZE.
0h = normal operation
1h = COLD_RESET
1STBY_I2C_CTRLR/W0h STBY control using I2C. Consolidated with STBY control via MODE/STBY pin. Refer to table in spec.
0h = normal operation
1h = STBY mode
0I2C_OFF_REQR/WSelfClrF0h When '1' is written to this bit: Trigger OFF request. When '0': No effect. Does self-clear.
0h = No effect
1h = Trigger OFF Request

7.6.43 DISCHARGE_CONFIG Register (Offset = 2Ah) [Reset = X]

DISCHARGE_CONFIG is shown in Figure 7-53 and described in Table 7-50.

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Figure 7-53 DISCHARGE_CONFIG Register
76543210
RESERVEDLDO4_DISCHARGE_ENLDO3_DISCHARGE_ENLDO2_DISCHARGE_ENLDO1_DISCHARGE_ENBUCK3_DISCHARGE_ENBUCK2_DISCHARGE_ENBUCK1_DISCHARGE_EN
R-XR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-50 DISCHARGE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6LDO4_DISCHARGE_ENR/W1h Discharge setting for LDO4
0h = No Discharge
1h = 250 Ω
5LDO3_DISCHARGE_ENR/W1h Discharge setting for LDO3
0h = No Discharge
1h = 250 Ω
4LDO2_DISCHARGE_ENR/W1h Discharge setting for LDO2
0h = No Discharge
1h = 200 Ω
3LDO1_DISCHARGE_ENR/W1h Discharge setting for LDO1
0h = No Discharge
1h = 200 Ω
2BUCK3_DISCHARGE_ENR/W1h Discharge setting for BUCK3
0h = No Discharge
1h = 125 Ω
1BUCK2_DISCHARGE_ENR/W1h Discharge setting for BUCK2
0h = No Discharge
1h = 125 Ω
0BUCK1_DISCHARGE_ENR/W1h Discharge setting for BUCK1
0h = No Discharge
1h = 125 Ω

7.6.44 INT_SOURCE Register (Offset = 2Bh) [Reset = 00h]

INT_SOURCE is shown in Figure 7-54 and described in Table 7-51.

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Figure 7-54 INT_SOURCE Register
76543210
INT_PB_IS_SETINT_LDO_3_4_IS_SETINT_LDO_1_2_IS_SETINT_BUCK_3_IS_SETINT_BUCK_1_2_IS_SETINT_SYSTEM_IS_SETINT_RV_IS_SETINT_TIMEOUT_RV_SD_IS_SET
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-51 INT_SOURCE Register Field Descriptions
BitFieldTypeResetDescription
7INT_PB_IS_SETR0h One or more sources of the INT present in register INT_PB
0h = No bits set in INT_PB
1h = One or more bits set in INT_PB
6INT_LDO_3_4_IS_SETR0h One or more sources of the INT present in register INT_LDO_3_4
0h = No bits set in INT_LDO_3_4
1h = One or more bits set in INT_LDO_3_4
5INT_LDO_1_2_IS_SETR0h One or more sources of the INT present in register INT_LDO_1_2
0h = No bits set in INT_LDO_1_2
1h = One or more bits set in INT_LDO_1_2
4INT_BUCK_3_IS_SETR0h One or more sources of the INT present in register INT_BUCK_3
0h = No bits set in INT_BUCK_3
1h = One or more bits set in INT_BUCK_3
3INT_BUCK_1_2_IS_SETR0h One or more sources of the INT present in register INT_BUCK_1_2
0h = No bits set in INT_BUCK_1_2
1h = One or more bits set in INT_BUCK_1_2
2INT_SYSTEM_IS_SETR0h One or more sources of the INT present in register INT_SYSTEM
0h = No bits set in INT_SYSTEM
1h = One or more bits set in INT_SYSTEM
1INT_RV_IS_SETR0h One or more sources of the INT present in register INT_RV
0h = No bits set in INT_RV
1h = One or more bits set in INT_RV
0INT_TIMEOUT_RV_SD_IS_SETR0h One or more sources of the INT present in register INT_TIMEOUT_RV_SD
0h = No bits set in INT_TIMEOUT_RV_SD
1h = One or more bits set in INT_TIMEOUT_RV_SD

7.6.45 INT_LDO_3_4 Register (Offset = 2Ch) [Reset = X]

INT_LDO_3_4 is shown in Figure 7-55 and described in Table 7-52.

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Figure 7-55 INT_LDO_3_4 Register
76543210
RESERVEDRESERVEDLDO4_UVLDO4_OCLDO4_SCGLDO3_UVLDO3_OCLDO3_SCG
R-XR-XR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-52 INT_LDO_3_4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5LDO4_UVR/W1C0h LDO4 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
4LDO4_OCR/W1C0h LDO4 Overcurrent Fault.
0h = No Fault detected
1h = Fault detected
3LDO4_SCGR/W1C0h LDO4 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
2LDO3_UVR/W1C0h LDO3 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
1LDO3_OCR/W1C0h LDO3 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
0LDO3_SCGR/W1C0h LDO3 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected

7.6.46 INT_LDO_1_2 Register (Offset = 2Dh) [Reset = X]

INT_LDO_1_2 is shown in Figure 7-56 and described in Table 7-53.

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Figure 7-56 INT_LDO_1_2 Register
76543210
RESERVEDRESERVEDLDO2_UVLDO2_OCLDO2_SCGLDO1_UVLDO1_OCLDO1_SCG
R-XR-XR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-53 INT_LDO_1_2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5LDO2_UVR/W1C0h LDO2 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
4LDO2_OCR/W1C0h LDO2 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
3LDO2_SCGR/W1C0h LDO2 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
2LDO1_UVR/W1C0h LDO1 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
1LDO1_OCR/W1C0h LDO1 Overcurrent Fault
0h = No Fault detected
1h = Fault detected
0LDO1_SCGR/W1C0h LDO1 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected

7.6.47 INT_BUCK_3 Register (Offset = 2Eh) [Reset = X]

INT_BUCK_3 is shown in Figure 7-57 and described in Table 7-54.

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Figure 7-57 INT_BUCK_3 Register
76543210
RESERVEDRESERVEDRESERVEDRESERVEDBUCK3_UVBUCK3_NEG_OCBUCK3_OCBUCK3_SCG
R-XR-XR-XR-XR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-54 INT_BUCK_3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5RESERVEDRX Reserved
4RESERVEDRX Reserved
3BUCK3_UVR/W1C0h BUCK3 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
2BUCK3_NEG_OCR/W1C0h BUCK3 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
1BUCK3_OCR/W1C0h BUCK3 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
0BUCK3_SCGR/W1C0h BUCK3 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected

7.6.48 INT_BUCK_1_2 Register (Offset = 2Fh) [Reset = 00h]

INT_BUCK_1_2 is shown in Figure 7-58 and described in Table 7-55.

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Figure 7-58 INT_BUCK_1_2 Register
76543210
BUCK2_UVBUCK2_NEG_OCBUCK2_OCBUCK2_SCGBUCK1_UVBUCK1_NEG_OCBUCK1_OCBUCK1_SCG
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-55 INT_BUCK_1_2 Register Field Descriptions
BitFieldTypeResetDescription
7BUCK2_UVR/W1C0h BUCK2 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
6BUCK2_NEG_OCR/W1C0h BUCK2 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
5BUCK2_OCR/W1C0h BUCK2 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
4BUCK2_SCGR/W1C0h BUCK2 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected
3BUCK1_UVR/W1C0h BUCK1 Undervoltage Fault. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_UV_MASK bit in register INT_MASK_UV is '1'
0h = No Fault detected
1h = Fault detected
2BUCK1_NEG_OCR/W1C0h BUCK1 Negative Overcurrent Fault
0h = No Fault detected
1h = Fault detected
1BUCK1_OCR/W1C0h BUCK1 Positive Overcurrent Fault
0h = No Fault detected
1h = Fault detected
0BUCK1_SCGR/W1C0h BUCK1 Short Circuit to Ground Fault
0h = No Fault detected
1h = Fault detected

7.6.49 INT_SYSTEM Register (Offset = 30h) [Reset = 00h]

INT_SYSTEM is shown in Figure 7-59 and described in Table 7-56.

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Figure 7-59 INT_SYSTEM Register
76543210
SENSOR_0_HOTSENSOR_1_HOTSENSOR_2_HOTSENSOR_3_HOTSENSOR_0_WARMSENSOR_1_WARMSENSOR_2_WARMSENSOR_3_WARM
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-56 INT_SYSTEM Register Field Descriptions
BitFieldTypeResetDescription
7SENSOR_0_HOTR/W1C0h TSD Hot detection for sensor 0
0h = No Fault detected
1h = Fault detected
6SENSOR_1_HOTR/W1C0h TSD Hot detection for sensor 1
0h = No Fault detected
1h = Fault detected
5SENSOR_2_HOTR/W1C0h TSD Hot detection for sensor 2
0h = No Fault detected
1h = Fault detected
4SENSOR_3_HOTR/W1C0h TSD Hot detection for sensor 3
0h = No Fault detected
1h = Fault detected
3SENSOR_0_WARMR/W1C0h TSD Warm detection for sensor 0. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_WARM_MASK bit in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
2SENSOR_1_WARMR/W1C0h TSD Warm detection for sensor 1. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_WARM_MASK bit in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
1SENSOR_2_WARMR/W1C0h TSD Warm detection for sensor 2. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_WARM_MASK bit in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected
0SENSOR_3_WARMR/W1C0h TSD Warm detection for sensor 3. Is automatically cleared upon a transition to INITIALIZE state, if corresponding *_WARM_MASK bit in register MASK_CONFIG is '1'
0h = No Fault detected
1h = Fault detected

7.6.50 INT_RV Register (Offset = 31h) [Reset = X]

INT_RV is shown in Figure 7-60 and described in Table 7-57.

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Figure 7-60 INT_RV Register
76543210
RESERVEDLDO4_RVLDO3_RVLDO2_RVLDO1_RVBUCK3_RVBUCK2_RVBUCK1_RV
R-XR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-57 INT_RV Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6LDO4_RVR/W1C0h RV event detected on LDO4 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
5LDO3_RVR/W1C0h RV event detected on LDO3 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
4LDO2_RVR/W1C0h RV event detected on LDO2 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
3LDO1_RVR/W1C0h RV event detected on LDO1 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
2BUCK3_RVR/W1C0h RV event detected on BUCK3 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
1BUCK2_RVR/W1C0h RV event detected on BUCK2 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected
0BUCK1_RVR/W1C0h RV event detected on BUCK1 rail during rail-turn-on, or after 4-5 ms during discharge checks prior to entering power sequence to ACTIVE state
0h = No RV detected
1h = RV detected

7.6.51 INT_TIMEOUT_RV_SD Register (Offset = 32h) [Reset = 00h]

INT_TIMEOUT_RV_SD is shown in Figure 7-61 and described in Table 7-58.

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Figure 7-61 INT_TIMEOUT_RV_SD Register
76543210
TIMEOUTLDO4_RV_SDLDO3_RV_SDLDO2_RV_SDLDO1_RV_SDBUCK3_RV_SDBUCK2_RV_SDBUCK1_RV_SD
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 7-58 INT_TIMEOUT_RV_SD Register Field Descriptions
BitFieldTypeResetDescription
7TIMEOUTR/W1C0h Is set if ShutDown occurred due to a TimeOut while: 1. Transitioning to ACTIVE state, and one or more rails did not rise past the UV level at the end of the assigned slot (and UV on this rail is configured as a SD fault). Which rail(s) is/are indicated by the *_UV bits in the INT_* registers. 2. Transitioning to STANDBY state, and one or more rails did not fall below the SCG level at the end of the assigned slot and discharge is enabled for that rail (which rail(s) is/are indicated by the corresponding RV_SD bit(s) in this register).
0h = No SD due to TimeOut occurred
1h = SD due to TimeOut occurred
6LDO4_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred
5LDO3_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO3 occurred
4LDO2_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO2 occurred
3LDO1_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on LDO1 occurred
2BUCK3_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK3 occurred
1BUCK2_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK2 occurred
0BUCK1_RV_SDR/W1C0h RV on LDO4 rail caused a shutdown during: 1. A transition to STANDBY state, this rail did not discharge at the end of the assigned slot and discharge is enabled for this rail 2. A transition to STANDBY state, RV was observed on this rail during the transition after this rail was disabled and discharge was enabled 3. A transition to ACTIVE state, RV was observed on this rail during the transition when this rail was OFF (rails are expected to be discharged before commencing the sequence to ACTIVE) 4. This rail did not discharge and therefore caused a Timeout-SD while attempting to discharge all rails at the start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets also set in this case)
0h = No SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred
1h = SD due to RV/DISCHARGE_TIMEOUT on BUCK1 occurred

7.6.52 INT_PB Register (Offset = 33h) [Reset = X]

INT_PB is shown in Figure 7-62 and described in Table 7-59.

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Figure 7-62 INT_PB Register
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDPB_REAL_TIME_STATUSPB_RISING_EDGE_DETECTEDPB_FALLING_EDGE_DETECTED
R-XR-XR-XR-XR-XR-1hR/W1C-0hR/W1C-0h
Table 7-59 INT_PB Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRX Reserved
6RESERVEDRX Reserved
5RESERVEDRX Reserved
4RESERVEDRX Reserved
3RESERVEDRX Reserved
2PB_REAL_TIME_STATUSR1h Deglitched (64-128ms) real-time status of PB pin. Valid only when EN/PB/VSENSE pin is configured as PB.
0h = Current deglitched status of PB: PRESSED
1h = Current deglitched status of PB: RELEASED
1PB_RISING_EDGE_DETECTEDR/W1C0h PB was released for > deglitch period (64-128ms) since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0').
0h = No PB-release detected
1h = PB-release detected
0PB_FALLING_EDGE_DETECTEDR/W1C0h PB was pressed for > deglitch period (64-128ms) since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0').
0h = No PB-press detected
1h = PB-press detected

7.6.53 USER_NVM_CMD_REG Register (Offset = 34h) [Reset = 00h]

USER_NVM_CMD_REG is shown in Figure 7-63 and described in Table 7-60.

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Figure 7-63 USER_NVM_CMD_REG Register
76543210
NVM_VERIFY_RESULTCUST_NVM_VERIFY_DONECUST_PROG_DONEI2C_OSC_ONUSER_NVM_CMD
R-0hR/W1C-0hR/W1C-0hR-0hR-0h
Table 7-60 USER_NVM_CMD_REG Register Field Descriptions
BitFieldTypeResetDescription
7NVM_VERIFY_RESULTR0h After an CUST_NVM_VERIFY_CMD is executed, this bit gives the result of the operation. (1 = fail, 0= pass). If '1', can only be cleared if a subsequent CUST_NVM_VERIFY_CMD passes.
0h = PASS
1h = FAIL
6CUST_NVM_VERIFY_DONER/W1C0h Is set to '1' after a CUST_NVM_VERIFY_CMD is executed. Remains '1' until W1C by user.
0h = Not yet done / not in progress
1h = Done
5CUST_PROG_DONER/W1C0h Is set to '1' after a CUST_PROG_CMD is executed. Remains '1' until W1C by user.
0h = Not yet done / not in progress
1h = Done
4I2C_OSC_ONR0h Is set set to '1' if an EN_OSC_DIY is received and the oscillator remains on in that case until a subsequent DIS_OSC_DIY is received. When '1' indicates that the OSC is ON regardless of ON_REQUEST. When '0', whether OSC is ON or OFF depends on whether we are waiting for an ON_REQUEST or not.
0h = OSC not controlled via I2C
1h = OSC unconditionally ON due to I2C command EN_OSC_DIY
3-0USER_NVM_CMDR0h Commands to enter DIY programming mode and program user NVM space. Always reads as 0.
6h = DIS_OSC_DIY
7h = CUST_NVM_VERIFY_CMD
9h = EN_OSC_DIY
Ah = CUST_PROG_CMD

7.6.54 POWER_UP_STATUS_REG Register (Offset = 35h) [Reset = 00h]

POWER_UP_STATUS_REG is shown in Figure 7-64 and described in Table 7-61.

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Figure 7-64 POWER_UP_STATUS_REG Register
76543210
POWER_UP_FROM_FSDPOWER_UP_FROM_EN_PB_VSENSECOLD_RESET_ISSUEDSTATERETRY_COUNTPOWER_UP_FROM_OFF
R/W1C-0hR/W1C-0hR/W1C-0hR-0hR-0hR/W1C-0h
Table 7-61 POWER_UP_STATUS_REG Register Field Descriptions
BitFieldTypeResetDescription
7POWER_UP_FROM_FSDR/W1C0h Is set if ON_REQ was triggered due to  FSD
0h = No power-up via FSD detected
1h = Power-up via FSD detected
6POWER_UP_FROM_EN_PB_VSENSER/W1C0h Is set if ON_REQ was triggered due to EN/PB/VSENSE pin
0h = No power-up via pin detected
1h = Power-up via pin detected
5COLD_RESET_ISSUEDR/W1C0h Is set if we received a COLD_RESET over pin or over I2C
0h = No COLD RESET received
1h = COLD RESET received either through pin or I2C
4-3STATER0h Indicates the current device state
0h = Transition state
1h = INITIALIZE
2h = STANDBY
3h = ACTIVE
2-1RETRY_COUNTR0h Reads the current retry count in the state machine. If RETRY_COUNT = 3 and is not masked, device does not power up.
0POWER_UP_FROM_OFFR/W1C0h Indicates if we powered up from OFF state (POR was asserted)
0h = OFF state not entered since the previous clearing of this bit
1h = OFF state was entered since the previous clearing of this bit

7.6.55 SPARE_2 Register (Offset = 36h) [Reset = 00h]

SPARE_2 is shown in Figure 7-65 and described in Table 7-62.

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Figure 7-65 SPARE_2 Register
76543210
SPARE_2_1SPARE_2_2SPARE_2_3SPARE_2_4SPARE_2_5SPARE_2_6SPARE_2_7SPARE_2_8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-62 SPARE_2 Register Field Descriptions
BitFieldTypeResetDescription
7SPARE_2_1R/W0h Spare bit in user non-NVM space
6SPARE_2_2R/W0h Spare bit in user non-NVM space
5SPARE_2_3R/W0h Spare bit in user non-NVM space
4SPARE_2_4R/W0h Spare bit in user non-NVM space
3SPARE_2_5R/W0h Spare bit in user non-NVM space
2SPARE_2_6R/W0h Spare bit in user non-NVM space
1SPARE_2_7R/W0h Spare bit in user non-NVM space
0SPARE_2_8R/W0h Spare bit in user non-NVM space

7.6.56 SPARE_3 Register (Offset = 37h) [Reset = 00h]

SPARE_3 is shown in Figure 7-66 and described in Table 7-63.

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Figure 7-66 SPARE_3 Register
76543210
SPARE_3_1
R/W-0h
Table 7-63 SPARE_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0SPARE_3_1R/W0h Spare bit in user non-NVM space

7.6.57 FACTORY_CONFIG_2 Register (Offset = 41h) [Reset = X]

FACTORY_CONFIG_2 is shown in Figure 7-67 and described in Table 7-64.

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Figure 7-67 FACTORY_CONFIG_2 Register
76543210
NVM_REVISION
R/W-X
Table 7-64 FACTORY_CONFIG_2 Register Field Descriptions
BitFieldTypeResetDescription
7-5NVM_REVISIONR/WX Specifies the version of the NVM configuration Note: This register can be programmed only by the manufacturer.
0h = V0
1h = V1 ...