ZHCSLJ2B September   2020  – July 2021 TPS62868 , TPS62869

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C InterfaceTiming Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 100% Duty Cycle Mode Operation
      4. 8.3.4 Start-up
      5. 8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Warning and Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Output Discharge
      3. 8.4.3 Start-Up Output Voltage and I2C Target Address Selection
        1. 8.4.3.1 TPS6286xxA Devices
        2. 8.4.3.2 TPS6286xxxC Devices
      4. 8.4.4 Select Output Voltage Registers (VID)
      5. 8.4.5 Power Good ( PG)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
    6. 8.6 Register Map
      1. 8.6.1 Target Address Byte
      2. 8.6.2 Register Address Byte
      3. 8.6.3 VOUT Register 1
      4. 8.6.4 VOUT Register 2
      5. 8.6.5 CONTROL Register
      6. 8.6.6 STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting The Output Voltage
        2. 9.2.2.2 Output Filter Design
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application – TPS6286x0A and TPS6286x0xC Devices
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Setting the Output Voltage
        2. 9.3.2.2 Output Filter Design
        3. 9.3.2.3 Inductor Selection
        4. 9.3.2.4 Capacitor Selection
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 支持资源
    4. 12.4 接收文档更新通知
    5. 12.5 Trademarks
    6. 12.6 术语表
    7. 12.7 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

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7.6 I2C InterfaceTiming Characteristics

PARAMETER (1) (2) TEST CONDITIONS MIN MAX UNIT
f(SCL) SCL Clock Frequency Standard mode 100 kHz
f(SCL) SCL Clock Frequency Fast mode 400 kHz
f(SCL) SCL Clock Frequency Fast mode plus 1 MHz
f(SCL) SCL Clock Frequency High-speed mode (write operation), CB – 100 pF max 3.4 MHz
f(SCL) SCL Clock Frequency High-speed mode (read operation), CB – 100 pF max 3.4 MHz
f(SCL) SCL Clock Frequency High-speed mode (write operation), CB – 400 pF max 1.7 MHz
f(SCL) SCL Clock Frequency High-speed mode (read operation), CB – 400 pF max 1.7 MHz
tBUF Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs
tBUF Bus Free Time Between a STOP and START Condition Fast mode 1.3 µs
tBUF Bus Free Time Between a STOP and START Condition Fast mode plus 0.5 µs
tHD, tSTA Hold Time (Repeated) START condition Standard mode 4 µs
tHD, tSTA Hold Time (Repeated) START condition Fast mode 600 ns
tHD, tSTA Hold Time (Repeated) START condition Fast mode plus 260 ns
tHD, tSTA Hold Time (Repeated) START condition High-speed mode 160 ns
tLOW LOW Period of the SCL Clock Standard mode 4.7 µs
tLOW LOW Period of the SCL Clock Fast mode 1.3 µs
tLOW LOW Period of the SCL Clock Fast mode plus 0.5 µs
tLOW LOW Period of the SCL Clock High-speed mode, CB – 100 pF max 160 ns
tLOW LOW Period of the SCL Clock High-speed mode, CB – 400 pF max 320 ns
tHIGH HIGH Period of the SCL Clock Standard mode 4 µs
tHIGH HIGH Period of the SCL Clock Fast mode 600 ns
tHIGH HIGH Period of the SCL Clock Fast mode plus 260 ns
tHIGH HIGH Period of the SCL Clock High-speed mode, CB – 100 pF max 60 ns
tHIGH HIGH Period of the SCL Clock High-speed mode, CB – 400 pF max 120 ns
tSU, tSTA Setup Time for a Repeated START Condition Standard mode 4.7 µs
tSU, tSTA Setup Time for a Repeated START Condition Fast mode 600 ns
tSU, tSTA Setup Time for a Repeated START Condition Fast mode plus 260 ns
tSU, tSTA Setup Time for a Repeated START Condition High-speed mode 160 ns
tSU, tDAT Data Setup Time Standard mode 250 ns
tSU, tDAT Data Setup Time Fast mode 100 ns
tSU, tDAT Data Setup Time Fast mode plus 50 ns
tSU, tDAT Data Setup Time High-speed mode 10 ns
tHD, tDAT Data Hold Time Standard mode 0 3.45 µs
tHD, tDAT Data Hold Time Fast mode 0 0.9 µs
tHD, tDAT Data Hold Time Fast mode plus 0 µs
tHD, tDAT Data Hold Time High-speed mode, CB – 100 pF max 0 70 ns
tHD, tDAT Data Hold Time High-speed mode, CB – 400 pF max 0 150 ns
tRCL Rise Time of SCL Signal Standard mode 1000 ns
tRCL Rise Time of SCL Signal Fast mode 20 + 0.1 CB 300 ns
tRCL Rise Time of SCL Signal Fast mode plus 120 ns
tRCL Rise Time of SCL Signal High-speed mode, CB – 100 pF max 10 40 ns
tRCL Rise Time of SCL Signal High-speed mode, CB – 400 pF max 20 80 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Standard mode 20 + 0.1 CB 1000 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Fast mode 20 + 0.1 CB 300 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Fast mode plus 120 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT High-speed mode, CB – 100 pF max 10 80 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT High-speed mode, CB – 400 pF max 20 160 ns
tFCL Fall Time of SCL Signal Standard mode 20 + 0.1 CB 300 ns
tFCL Fall Time of SCL Signal Fast mode 300 ns
tFCL Fall Time of SCL Signal Fast mode plus 120 ns
tFCL Fall Time of SCL Signal High-speed mode, CB – 100 pF max 10 40 ns
tFCL Fall Time of SCL Signal High-speed mode, CB – 400 pF max 20 80 ns
tRDA Rise Time of SDA Signal Standard mode 1000 ns
tRDA Rise Time of SDA Signal Fast mode 20 + 0.1 CB 300 ns
tRDA Rise Time of SDA Signal Fast mode plus 120 ns
tRDA Rise Time of SDA Signal High-speed mode, CB – 100 pF max 10 80 ns
tRDA Rise Time of SDA Signal High-speed mode, CB – 400 pF max 20 160 ns
tFDA Fall Time of SDA Signal Standard mode 300 ns
tFDA Fall Time of SDA Signal Fast mode 20 + 0.1 CB 300 ns
tFDA Fall Time of SDA Signal Fast mode plus 120 ns
tFDA Fall Time of SDA Signal High-speed mode, CB – 100 pF max 10 80 ns
tFDA Fall Time of SDA Signal High-speed mode, CB – 400 pF max 20 160 ns
tSU, tSTO Setup Time of STOP Condition Standard mode 4 µs
tSU, tSTO Setup Time of STOP Condition Fast mode 600 ns
tSU, tSTO Setup Time of STOP Condition Fast mode plus 260 ns
tSU, tSTO Setup Time of STOP Condition High-Speed mode 160 ns
CB Capacitive Load for SDA and SCL Standard mode 400 pF
CB Capacitive Load for SDA and SCL Fast mode 400 pF
CB Capacitive Load for SDA and SCL Fast mode plus 550 pF
CB Capacitive Load for SDA and SCL High-Speed mode 400 pF
(1) All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.
(2) For bus line loads CB between 100 pF and 400 pF, the timing parameters must be linearly interpolated.