ZHCSE52B September 2015 – May 2019 TPS57140-EP
PRODUCTION DATA.
Layout is a critical portion of good power-supply design. There are several signals paths that conduct quickly changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To reduce these problems, bypass the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66 for a PCB layout example. Tie the GND pin directly to the thermal pad under the IC and the exposed thermal pad.
Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Route the PH pin to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, locate the catch diode and output inductor very close to the PH pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling. For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC and route the traces to minimize their lengths. Place the additional external components approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout produces good results and can serve as a guideline.