Figure 7-11 shows an equivalent model for the TPS54618C-Q1 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 245 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R0 and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the R_L with a current source with the appropriate load step amplitude and step rate in a time domain analysis.

Figure 7-11 Small Signal Model for Loop Response

Figure 7-11 is a simple, small-signal model that can be used to understand how to design the frequency compensation. The TPS54618C-Q1 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 7-11) is the power stage transconductance. The gm for the TPS54618C-Q1 is 25 A/V. The low frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 12. As the load current increases and decreases, the low frequency gain decreases and increases, respectively. This variation with load can seem problematic at first glance, but the dominant pole moves with load current. The combined effect is highlighted by the dashed line in the right half of Figure 7-13. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

Figure 7-12 Small Signal Model for Peak Current Mode Control

Figure 7-13 Frequency Response Model for Peak Current Mode Control

Equation 11.

Equation 12.

Equation 13.

Equation 14.