ZHCSLU7A September   2020  – August 2021 TPS54618C-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Simple Small Signal Model for Peak Current Mode Control
      2. 7.4.2 Small Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step One: Select the Switching Frequency
        2. 8.2.2.2 Step Two: Select the Output Inductor
        3. 8.2.2.3 Step Three: Choose the Output Capacitor
        4. 8.2.2.4 Step Four: Select the Input Capacitor
        5. 8.2.2.5 Step Five: Choose the Soft-Start Capacitor
        6. 8.2.2.6 Step Six: Select the Bootstrap Capacitor
        7. 8.2.2.7 Step Eight: Select Output Voltage and Feedback Resistors
          1. 8.2.2.7.1 Output Voltage Limitations
        8. 8.2.2.8 Step Nine: Select Loop Compensation Components
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Developmental Support
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open-drain or collector output of a power-on reset pin of another device. Figure 7-3 shows the sequential method. The power good is coupled to the EN pin on the TPS54618C-Q1 which enables the second power supply once the primary supply reaches regulation.

Ratio-metric start-up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must be doubled in Equation 4. The ratio-metric method is shown in Figure 7-5.

GUID-89D24B7E-96CA-4E42-865C-5EBC8F9A342E-low.gif
 
 
Figure 7-3 Sequential Start-Up Sequence
GUID-8F38D914-2B54-4D7D-A871-A88D62F68F9C-low.gifFigure 7-4 Sequential Start-Up
Using EN and PWRGD
GUID-D65A67F5-B7BB-4012-9B34-3EFA16FCABB0-low.gifFigure 7-5 Schematic for Ratio-Metric Start-Up Sequence
GUID-8CEDA1EF-10B8-4A3E-9FDA-941A7FC78D4E-low.gif
   
   
 
 
 
Figure 7-6 Ratio-Metric Start-Up

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 7-7 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and Vout2. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 5 through Equation 7 for ΔV. Equation 7 results in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.1 V for a complete hand off to the internal voltage reference as shown in Figure 7-6.

Equation 5. GUID-79EC6D83-E233-4AF1-82C4-A4B0C13926E2-low.gif

Equation 6. GUID-6B5FF79F-C2C1-4D4F-BDE8-50FFB8260A32-low.gif

Equation 7. GUID-89045C47-05B8-44C6-B054-88AD03E8B7F0-low.gif

Equation 8. GUID-70F371F9-C512-49A1-B689-75B06050A73F-low.gif

GUID-5A9C0835-64C2-40A8-BE76-642685BC3612-low.gifFigure 7-7 Ratio-Metric and Simultaneous Start-Up Sequence
GUID-3A6D36A7-B3FA-4906-B373-D76A6C0A9A25-low.gif
  
  
Figure 7-8 Ratio-Metric Start-Up Using Coupled SS/TR Pins