ZHCSOL9B March   2013  – August 2021 TPS53511

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Soft Start and Pre-Biased Soft-Start Function
      4. 7.3.4 Power Good
      5. 7.3.5 Output Discharge Control
      6. 7.3.6 Current Protection
      7. 7.3.7 Overvoltage/Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
        6. 8.2.2.6 Output Voltage Setting Resistors Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Considerations
      1. 10.1.1 Thermal Information
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.3 Soft Start and Pre-Biased Soft-Start Function

The soft-start time function is adjustable. When the EN pin becomes high, 2-µA current begins charging the capacitor, which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow-start time is shown in Equation 1. The VFB voltage is 0.765 V and SS pin source current is 2 µA.

Equation 1. GUID-2C8F2BEC-F637-469F-862C-3C37A111B435-low.gif

where

  • CSS is the value of the capacitor connected between the SS pin and GND.
  • CSS is expressed in nF.

This unique circuit prevents current from being pulled from the output during start-up if the output is pre-biased. When the soft start commands a voltage higher than the pre-bias level (internal soft-start voltage becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low-side FET gate driver pulses with a narrow on time. It then increments the on time on a cycle-by-cycle basis until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and makes sure the output voltage (the VO pin) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.