ZHCS936A May   2012  – February 2019 TPS53014

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      典型应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 Auto-Skip Eco-Mode Control
      3. 7.3.3 Drivers
      4. 7.3.4 5-Volt Regulator
      5. 7.3.5 Soft Start and Pre-Biased Soft Start
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Over/Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Detailed Design Procedure
        1. 8.1.1.1 Component Selection
          1. 8.1.1.1.1 Inductor
          2. 8.1.1.1.2 Output Capacitor
          3. 8.1.1.1.3 Input Capacitor
          4. 8.1.1.1.4 Bootstrap Capacitor
          5. 8.1.1.1.5 VREG5 Capacitor
          6. 8.1.1.1.6 Choose Output Voltage Resistors
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10器件和文档支持
    1. 10.1 接收文档更新通知
    2. 10.2 社区资源
    3. 10.3 商标
    4. 10.4 静电放电警告
    5. 10.5 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6.4-µA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.773 V and SS pin source current is 6.4-µA.

Equation 2. TPS53014 eq2_slvsb8f1.gif

The TPS53014 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VO) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.