ZHCSQC2A November   2015  – July 2022 TPS51216-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDDQ Switch Mode Power Supply Control
      2. 8.3.2 VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3 Soft-Start and Powergood
      4. 8.3.4 Power State Control
      5. 8.3.5 Discharge Control
      6. 8.3.6 VTT Overcurrent Protection
      7. 8.3.7 V5IN Undervoltage Lockout (UVLO) Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 D-CAP Mode
      2. 9.1.2 Light-Load Operation
      3. 9.1.3 VTT and VTTREF
      4. 9.1.4 VDDQ Overvoltage and Undervoltage Protection
      5. 9.1.5 VDDQ Overcurrent Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 List of Materials
        2. 9.2.2.2 External Components Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.1.1 D-CAP Mode

Figure 9-1 shows a simplified model of D-CAP mode architecture.

GUID-82C04E30-E10D-4DBB-9604-56BD47B0FCE7-low.gifFigure 9-1 Simplified D-CAP Model

The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. The D-CAP mode offers flexibility on output inductance and capacitance selections and provides ease-of-use with a low external component count. However, it requires a sufficient amount of output ripple voltage for stable operation and good jitter performance.

The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, ƒ0 defined in Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.

Equation 1. GUID-77E4B3FE-59A6-4B9B-B4C1-4353B8FC3734-low.gif

where

  • ESR is the effective series resistance of the output capacitor
  • COUT is the capacitance of the output capacitor
  • ƒsw is switching frequency

Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP mode is the down-slope angle of the VDDQSNS ripple voltage. Figure 9-2 shows, in the same noise condition, a jitter is improved by making the slope angle larger.

GUID-D67EB8D4-69BD-44C8-8D03-90D75E297A8F-low.gifFigure 9-2 Ripple Voltage Slope and Jitter Performance

For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as shown in Figure 9-2 and Equation 2.

Equation 2. GUID-1AF9FAA1-0280-433D-A127-88A59AF74679-low.gif

where

  • VOUT is the VDDQ output voltage
  • LX is the inductance