ZHCSMM1C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

VVS = 11 V to 36 V, VVDD = 3.0 V to 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENT
VDS_Clamp CHx VDS clamp voltage  FET current = 10 mA, VS = 24 V 40 44 50 V
VDS_Clamp CHx VDS clamp voltage FET current = 10 mA, VS = 19 V 40 44 50 V
VDS_Clamp CHx VDS clamp voltage FET current = 10 mA, VS = 10 V 33 37 41 V
VS_UVPF VS undervoltage protection falling Measured with respect to the GND pin of the device, All channels ON Output FETs turned off at VS less than this threshold. 8.6 9 9.3 V
VS_UVPR VS undervoltage protection recovery rising Measured with respect to the GND pin of the device, All channels ON Output FETs turned ON at VS more than this threshold. 9.5 10 10.3 V
VS_UVPRH VS undervoltage protection deglitch time Time from triggering the UVP fault to FET turn-off 15 20 25 µs
VS_UVWF VS undervoltage warning falling Measured with respect to the GND pin of the device, Reported in VS_UV_WRN register bit when below this threshold 12 12.5 13.5 V
VS_UVWR VS undervoltage warning recovery rising Measured with respect to the GND pin of the device,  VS_UV_WRN register bit cleared when below this threshold and register read 11.2 13.5 15.8 V
VS_UVLOF VS  undervoltage lockout falling Measured with respect to the GND pin of the device Device will hit POR and READY pin will be pulled low 3.0 V
VS,UVLOR VS undervoltage lockout rising Measured with respect to the GND pin of the device READY pin will go high 2.7 3 3.3 V
VDD,UVLOF VDD  undervoltage lockout falling Measured with respect to the GND pin of the device 2.7 2.8 2.9 V
VDD,UVLOR VDD undervoltage lockout rising Measured with respect to the GND pin of the device 2.8 2.88 2.98 V
ILNOM Continuous load current, per channel All channels enabled, TAMB = 85°C 1.6 A
Two channels enabled, TAMB = 85°C 2.5 A
IOUT,LEAKX Leakage current from OUT to GND in OFF state Vs = VOUT < 36 V, Switch and all diagnostics disabled, measured into the OUTx pin 40 µA
IOUT(OFF) Output leakage current (per channel) VS <= 36 V, VOUT = 0
Channel disabled, diagnostics disabled Tj <= 125°C		 0 0.8 10 µA
VDD IQ VDD quiescent current, SCLK ON, all diagnostics disabled,(WB_OFF, WB_ON, SHRT_VS, ADC) external VDD VS ≤ 36 V, VDD = 5.5 V
All channels enabled,  IOUTx = 0 A		 1.3 1.6 mA
VDD IQ VDD quiescent current, SCLK ON, all diagnostics disabled,(WB_OFF, WB_ON, SHRT_VS, ADC) external VDD VS ≤ 36 V, VDD = 3.0 V
All channels enabled,  IOUTx = 0 A		 1 1.2 mA
VDD IQ VDD quiescent current, SCLK off, all diagnostics disabled ((WB_OFF, WB_ON, SHRT_VS), ADC enabled and converting, external VDD VS ≤ 36 V, VDD = 5.5 V
All channels enabled,  IOUTx = 0 A		 1.2 1.6 mA
VS IQ VS quiescent current, SCLK off, all diagnostics disabled,(WB_OFF, WB_ON, SHRT_VS, ADC) internal VDD VS ≤ 36 V, 
All channels enabled,  IOUTx = 0 A		 2.8 3.2 mA
VS IQ VS quiescent current, SCLK off, all diagnostics (WB_OFF, WB_ON, SHRT_VS, ADC) enabled, external VDD VS ≤ 36 V, VDD = 3.0 V
All channels enabled,  IOUTx = 0 A		 1.7 2.5 mA
VS IQ VS quiescent current, SCLK off, all diagnostics (WB_OFF, WB_ON, SHRT_VS, ADC) disabled, RCB enabled, external VDD VS ≤ 36 V, VDD = 3.0 V
All channels enabled,  IOUTx = 0 A		 1.4 2.45 mA
Ileak_LG Leakage current out of the output pins with the GND of IC disconnected, Load ground connected to supply ground VS≤ 30 V, VDD = 5.5 V, RL = 24 Ω
All channels enabled		 0.8 0.9 mA
RON CHARACTERISTICS
RON On-resistance
(Includes MOSFET and package)		 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 = 200 mA TJ = 25°C 72 mΩ
TJ = 125°C 110 mΩ
On-resistance when 2 channels are paralleled
(Includes MOSFET and package)		 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 > 200 mA.
VOUT1 tied to VOUT2		 TJ = 25°C 33 mΩ
TJ = 125°C 55 mΩ
VDD_REG CHARACTERISTICS
VVDD VDD Output voltage (Internal regulator enabled) 6 V ≤ VS ≤ 36 V, IVDD < 20 mA Includes load and line regulation across the range. 3.1 3.3 3.6 V
LRVDD Load regulation of internal VDD regulator when enabled 6 V ≤ VS ≤ 36 V, IVDD < 20 mA 0.95 V/A
LRtran_VDD Load transient regulation of internal VDD regulator when enabled 6 V ≤ VS ≤ 36 V, IVDD <step from 5 mA to 15 mA in 10 μs 1 uF 10 mV
ICL_VDD Current Limit of internal regulator  6 V ≤ VS ≤ 36 V 25 50 mA
CURRENT SENSE CHARACTERISTICS
ISNSI CHx Current sense ratio
IOUTx / ISNS		 IOUTX = 1 A, Range = 2.4 A IOUTX = 1 A 1160
ISNSI CHx CHx Current sense current Current Sense Diagnostic Enabled, RSNS = 1kΩ IOUTx = 2 A 1.69 1.73 1.77 mA
IOUT1 = 1 A 0.834 0.862 0.890 mA
IOUT1 = 500 mA 0.410 0.424 0.45 mA
IOUT1 = 200 mA 0.151 0.168 0.184 mA
IOUT1 = 100 mA 0.068 0.081 0.092 mA
IOUT1 = 50 mA 0.02 0.037 0.054 mA
ISNSI CHx CHx Current sense current Current Sense Diagnostic Enabled, RSNS = 1kΩ IOUT1 = 20 mA 0.005 0.010 0.028 mA
ISNSI CHx CHx Current sense current Current Sense Diagnostic Enabled, RSNS = 1kΩ IOUT1 = 10 mA 0.002 0.005 0.008 mA
ISNSI CHx CHx Current sense current Current Sense Diagnostic Enabled, RSNS = 1kΩ IOUT1 = 5 mA 0.000 0.002 0.004 mA
ADC Performance Characteristics
VADCEFfHI ADC refernce voltage 2.72 2.8 2.85 V
Tconv1 ADC sample update time in each measurement 128 µs
SNS CHARACTERISTICS
TSNSout1 TSNS output TJ = –40°C 2.57 V
TSNSout2 TSNS output TJ = 25°C 2.17 V
TSNSout3 TSNS output TJ = 125°C 1.55 V
VOUTSNS_CHx VOUTSNS output VOUT_CHx = 20 V 1.87 V
CURRENT LIMIT CHARACTERISTICS
ICLx CHx ICL current limitation level, H version Regulated current at short circuit RL < 200 mohms when Enabled. VDD = 3.3 V. Setting = 2.45 A 2.06 2.45 2.84 A
Setting = 2.26 A 2.01 2.26 2.88 A
Setting = 2.07 A 1.74 2.07 2.4 A
Setting = 1.9 A 1.6 1.9 2.3 A
Setting =1.71 A 1.42 1.71 1.94 A
Setting = 1.52 A 1.2 1.52 1.78 A
Setting = 1.33 A 1.06 1.33 1.6 A
Setting = 1.15 A 0.94 1.15 1.36 A
Setting = 0.96 A 0.78 0.96 1.1 A
Setting = 0.86 A 0.72 0.86 1.02 A
Setting = 0.76 A 0.64 0.76 0.88 A
Setting = 0.67 A 0.53 0.67 0.78 A
Setting = 0.57 A 0.47 0.57 0.65 A
Setting = 0.48 A 0.4 0.48 0.55 A
Setting = 0.38 A 0.3 0.38 0.45 A
Setting = 0.29 A 0.22 0.29 0.39 A
ICLx CHx ICL current limitation level Regulated current at short circuit RL < 200 mohms when Enabled. VDD = 3.3 V. Setting = 2.2 A 1.85 2.2 2.55 A
Setting = 1.9 A 1.6 1.9 2.3 A
Setting = 1.75 A 1.5 1.75 2.05 A
Setting = 1.6 A 1.35 1.6 1.85 A
Setting =1.5 A 1.19 1.5 1.75 A
Setting = 1.25 A 1 1.25 1.5 A
Setting = 1.1 A 0.9 1.1 1.3 A
Setting = 1 A 0.85 1 1.15 A
Setting = 0.85 A 0.72 0.85 1 A
Setting = 0.72 A 0.62 0.72 0.82 A
Setting = 0.67 A 0.53 0.67 0.78 A
Setting = 0.56 A 0.47 0.56 0.63 A
Setting = 0.48 A 0.4 0.48 0.55 A
Setting = 0.4 A 0.32 0.4 0.47 A
Setting = 0.33 A 0.26 0.33 0.39 A
Setting = 0.25 A 0.19 0.25 0.33 A
ICL_LINPK Overcurrent limit threshold Threshold before current limiting - Overload condition Setting = 2.2 A VVS – VVOUT < 1 V 2.75 A
ICL_LINPK Overcurrent limit threshold Threshold before current limiting - Overload Conditions Setting = 0.85 A VVS-VVOUT < 1V 1.1 A
ICL_PK1 Peak current before regulation while enabling switch into 100 mohm load TJ = –40°C to 125°C VS = 24 V, Minimum inductance = 2.2 µH Settting = 2.2 A 10 A
ICL_PK2 Peak current threshold when short is applied while switch enabled TJ = –40°C to 125°C VS = 24 V, Minimum inductance = 2.2 µH Settting = 2.2 A 9.4 A
ICL_P Parallel ICL Current Limitation Level Regulated current at short circuit RL < 200 mohms when Enabled Settting = 2.2 A 4.3 A
ICL_PK1_P Paralled Peak current enabling into permanent short TJ = –40°C to 125°C VS = 24V, Minimum inductance = 2.2 µH Settting = 2.2 A 6.4 A
ICL,PARALLEL Paralled Channels Current Limit Accuracy Multiplier  VOUT1 tied to VOUT2, parallel channel mode enabled Settting = 2.2 A 0.9 1.1
FAULT CHARACTERISTICS
IWB_ON_TH Wire-break (WB) or Open-load (OL) detection on-state threshold Switch enabled, WB_ON_CHx = enabled WB_ON_TH_= 000 0.38 0.49 0.61 mA
IWB_OFF Off State Wirebreak or Open-load (OL) detection internal pullup current Switch disabled, WB_OFF_CHx = enabled WB_PU=00 38 51 64 µA
VSHRT_VS_TH Off state short to VS detection voltage Channel Disabled, off-state short_VS diagnostics enabled 12.0 V
VWB_OFF_PU Off state WireBreak (WB) or Open-load (OL) detection pull up current source voltage Channel Disabled, off-state wire-break diagnostics enabled 6.7 V
VWB_OFF_TH Off state WireBreak (WB) or Open-load (OL) detection voltage Channel Disabled, off-state wire-break diagnostics enabled 5.6 6 6.5 V
tRCB_DGL CHx RCB Fault Deglitch time Channel Enabled, RCB enabled 1.2 ms
TABS Thermal shutdown 160 185 210 °C
TOTW Thermal shutdown warning 110 130 150 °C
THYS Thermal shutdown hysteresis 20 27 35 °C
Vol_FLT Fault low-output voltage IFLT = 2 mA, sink current into the pin 0.4 V
tRETRY Retry time Time from thermal shutdown until switch re-enable. 0.6 ms
tRCB_F Reverse current protection comparator delay Time from VS – VOUT < 50 mV overdrive to FET gate off 1.6 2 2.4 µs
VRCB_F V(VS) – V(OUT) threshold for
reverse protection comparator,
falling		 -104 -64 -23 mV
tRCB_comp_reset RCB internal comparator reset interval 100 ms
VRCB_pu RCBx FET gate voltage 6 7 V
VRCB_R V(VS) – V(OUT) threshold for
reverse protection comparator,
rising		 28 45 58 mV
DIGITAL INPUT PIN CHARACTERISTIC
VIH, DIG DIG pin Input voltage high-level 3.0 V ≤ VDD ≤ 5.5 V 0.7 × VVDD V
VIL, DIG DIG pin Input voltage low-level 3.0 V ≤ VDD ≤ 5.5 V 0.3 × VVDD V
RREG_EN Internal pullup resistance for REG_EN pin 1 MΩ
RDIGx Internal pulldown resistor 0.7 1 2.0 MΩ
IIH, DIG Input current high-level VDIG = 5 V 5 µA
DIGITAL OUTPUT PIN CHARACTERISTICS
VOH Output Logic High Voltage Drop READY Pin current = –4 mA -0.5 V
VOL_SDO Output Logic Low Voltage  SDO Pin current = –4 mA 0.2 V
VOL_FLT Output Logic Low Voltage  FLT Pin current = –4 mA 0.4 V
LED DRIVER CHARACTERISTICS
Vdrop_HL14 LED High Side / Low side drop Channels 1 and 4 I_LED (average current over 4 phases) = 4 mA, LED switch current = 16 mA 0.2 V
Vdrop_HL23 LED High Side / Low side drop Channels 2 and 3 I_LED (average current over 4 phases) = 4 mA, LED switch current = 32 mA 0.2 V
fPWM_LED LED driver PWM frequency 1000  Hz