ZHCSMM1C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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8.3.6.5 Off State Wire-Break Detection

While the switch disabled and WB_OFF_CHx_EN high, an internal comparator watches the condition of VOUT. The TPS274C65 includes a current source connected to VOUT controlled by the DIA_EN signal. So, if the load is disconnected (open load condition) or there is a short to battery the VOUT voltage will be pulled towards VS. In either of these events, the internal comparator will measure VOUT as higher than the open load threshold (VOL,off) and a fault is indicated on the FLT pin and on the SNS pin. No external component are required in most cases, however if there is external pull-down resistor to GND on VOUT, an additional external pull-up resistor might be necessary to bias VOUT appropriately.

The comparator and detection circuitry is only enabled when EN = LOW. Open load will be indicated on the FLT pin even if WB_OFF_CHx_EN is set low, but will need an external pull-up resistor (and potentially a switch). Open load fault signaling on the SNS is enabled only if WB_OFF_CHx_EN is set HI.

While the switch is disabled, the fault indication mechanisms will continuously represent the present status. For example, if VOUT decreases from greater than VOL to less than VOL, the fault indication is reset. Additionally, the fault indication is reset upon WB_OFF_CHx_EN = 0 or the rising edge of EN.

GUID-20231017-SS0I-PKWT-BMM2-5B8KPXQ2JP63-low.svg Figure 8-36 Open Load Detection Circuit
GUID-20231017-SS0I-C56R-DSNJ-WCGKVS1GJVLC-low.svg Figure 8-37 Off-State Open Load Detection Timing
GUID-20210606-CA0I-HBKL-4NQ1-5RM7JHXZG8W5-low.svg Figure 8-38 Off-State Open Load Detection Timing