ZHCSHY9 April   2018 TPS22810-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     简化原理图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical DC Characteristics
    8. 6.8 Typical AC Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 On and Off Control
      2. 8.3.2 Quick Output Discharge (QOD)
        1. 8.3.2.1 QOD when System Power is Removed
        2. 8.3.2.2 Internal QOD Considerations
      3. 8.3.3 EN/UVLO
      4. 8.3.4 Adjustable Rise Time (CT)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 ON and OFF Control
      2. 9.1.2 Input Capacitor (Optional)
      3. 9.1.3 Output Capacitor (Optional)
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shutdown Sequencing During Unexpected Power Loss
        2. 9.2.2.2 VIN to VOUT Voltage Drop
        3. 9.2.2.3 Inrush Current
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

EN/UVLO

EN/UVLO controls the ON and OFF state of the internal MOSFET, as an input pin. In its high state, the internal MOSFET is enabled. A low on this pin turns off the internal MOSFET. High and Low levels are specified in the parametric table of the datasheet.

A voltage VEN/UVLO< VENF on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while voltage below VSHUTF takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power loss.

The EN/UVLO pin can be directly driven by a 1.8 V, 3.3 V or 5 V general purpose output pin.

The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (2.5 μs typical) for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.

The undervoltage lock out (UVLO) threshold can be programmed by using an external resistor divider from supply VIN terminal to EN/UVLO terminal to GND shown in Figure 18. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off. If the programmable UVLO function is not needed, the EN/UVLO terminal must be connected to the VIN terminal. EN/UVLO terminal must not be left floating.

The device also implements internal UVLO circuitry on the VIN terminal. The device disables when the VIN terminal voltage falls below internal UVLO Threshold (VUVF). The internal UVLO threshold has a hysteresis (VUVRhyst). See Figure 19 and Figure 20.

TPS22810-Q1 ConfigUVLOwithExternalResistor_SLVSDJ0.gifFigure 18. Configuring UVLO with External Resistor Network
TPS22810-Q1 Using18V33VGPIOdirectsignal_SLVSDJ0.gifFigure 19. Using 1.8 V/3.3 V GPIO Signal Directly from Processor
TPS22810-Q1 DefaultUVLOthreshold_SLVSDJ0.gifFigure 20. Default UVLO Threshold VUVR Using No Additional External Components