ZHCSMX0B September   2019  – December 2020 TPA6304-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Bridge-Tied Load (BTL), BD
      2. 6.6.2 Parallel Bridge-Tied Load (PBTL)
      3. 6.6.3 Bridge-Tied Load (BTL), 1SPW
      4. 6.6.4 Bridge-Tied Load (BTL), 384 kHz, BD
      5. 6.6.5 Bridge-Tied Load (BTL), 384 kHz, 1SPW
  7. 7 Parameter measurement information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Single-Ended Analog Inputs
      2. 7.3.2  Gain Control
      3. 7.3.3  Class-D Operation and Spread Spectrum Control
        1. 7.3.3.1 High Frequency Pulse Width Modulator (PWM)
        2. 7.3.3.2 Clock Synchronization
        3. 7.3.3.3 Spread Spectrum Control
      4. 7.3.4  Gate Drive
      5. 7.3.5  Power FETs
      6. 7.3.6  Load Diagnostics
        1. 7.3.6.1 DC Load Diagnostics
          1. 7.3.6.1.1 Automatic DC Load Diagnostics at Device Initialization
          2. 7.3.6.1.2 Automatic DC Load Diagnostics During Hi-Z to MUTE or PLAY Transition
          3. 7.3.6.1.3 Manual Start of DC Load Diagnostics
          4. 7.3.6.1.4 Short-to-Ground
          5. 7.3.6.1.5 Short-to-Power
          6. 7.3.6.1.6 Shorted Load and Open Load
          7. 7.3.6.1.7 Line Output Diagnostics
        2. 7.3.6.2 AC Load Diagnostics
          1. 7.3.6.2.1 Operating Principal
          2. 7.3.6.2.2 Stimulus
          3. 7.3.6.2.3 Load Impedance
          4. 7.3.6.2.4 Tweeter Detection
          5. 7.3.6.2.5 Operation
      7. 7.3.7  Power Supply
        1. 7.3.7.1 Power-Supply Sequence
          1. 7.3.7.1.1 Power-Up Sequence
          2. 7.3.7.1.2 Power-Down Sequence
      8. 7.3.8  Device Initialization and Power-On-Reset (POR)
      9. 7.3.9  Protection and Monitoring
        1. 7.3.9.1 Over Current Protection
        2. 7.3.9.2 DC Detect
        3. 7.3.9.3 Load Current Limit
        4. 7.3.9.4 Clip Detect
        5. 7.3.9.5 Temperature Protection and Monitoring
          1. 7.3.9.5.1 Over Temperature Shutdown (OTSD)
          2. 7.3.9.5.2 Over Temperature Warning (OTW)
          3. 7.3.9.5.3 Thermal Gain Foldback (TGFB)
        6. 7.3.9.6 Power Failures
        7. 7.3.9.7 Load Dump Protection
      10. 7.3.10 Hardware Control Pins
        1. 7.3.10.1 FAULT Pin
        2. 7.3.10.2 STANDBY Pin
        3. 7.3.10.3 GPIO Pins
        4. 7.3.10.4 WARNING
        5. 7.3.10.5 MUTE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal Reporting Signals
        1. 7.4.1.1 Fault Signal
        2. 7.4.1.2 Warning Signal
        3. 7.4.1.3 Clip Detect Signal
      2. 7.4.2 Device States and Flags
        1. 7.4.2.1 Audio Channel States
          1. 7.4.2.1.1 PROTECTIVE SHUTDOWN with AUTO RECOVERY State
          2. 7.4.2.1.2 PROTECTIVE SHUTDOWN State
            1. 7.4.2.1.2.1 Clear Fault
        2. 7.4.2.2 Status and Memory Registers
          1. 7.4.2.2.1 Status Registers
          2. 7.4.2.2.2 Memory Registers
      3. 7.4.3 Fault Events
        1. 7.4.3.1 Overview
        2. 7.4.3.2 Power Fault Events
          1. 7.4.3.2.1 DVDD POR
          2. 7.4.3.2.2 VBAT Over Voltage Fault
          3. 7.4.3.2.3 VBAT Under Voltage Fault
          4. 7.4.3.2.4 PVDD Over Voltage Fault
          5. 7.4.3.2.5 PVDD Under Voltage Fault
          6. 7.4.3.2.6 GVDD Fault
        3. 7.4.3.3 Over Temperature Shut Down (OTSD) Event
        4. 7.4.3.4 Over Current Shut Down (OCSD) Event
        5. 7.4.3.5 DC Fault Event
        6. 7.4.3.6 Load Current Fault Event
        7. 7.4.3.7 Invalid Clock Fault Event
      4. 7.4.4 Warning Events
        1. 7.4.4.1 Overview
        2. 7.4.4.2 Over Temperature Warning Event
        3. 7.4.4.3 Thermal Gain Foldback Warning Event
        4. 7.4.4.4 Load Current Warning Event
        5. 7.4.4.5 Clip Warning Event
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Communication Bus
        1. 7.5.1.1 I2C Address Selection
      2. 7.5.2 I2C Bus Protocol
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 AM Radio Avoidance
      2. 8.1.2 Parallel BTL Operation (PBTL)
      3. 8.1.3 Reconstruction Filter Design
      4. 8.1.4 Bootstrap Capacitors
      5. 8.1.5 Line Driver Applications
    2. 8.2 Typical Applications
      1. 8.2.1 BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Hardware Design Procedure
      2. 8.2.2 PBTL Application
        1. 8.2.2.1 Detailed Hardware Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Electrical Connection of Thermal Pad and Heat Sink
      2. 10.1.2 General Considerations
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1 Registers

Table 7-10 lists all registers, their functionality and default values. All register offset addresses not listed in Register Map should be considered as reserved locations and the register contents should not be modified.

Table 7-10 Register Map
Offset Acronym Register Name Section
0x1 Mode Control Mode Control Register Go
0x2 Misc Control 1 Miscellaneous Control Register 1 Go
0x3 Misc Control 2 Miscellaneous Control Register 2 Go
0x4 Channel State Control Channel State Control Register Go
0x5 DC LDG Ctrl 1 DC Load Diagnostics Control Register 1 Go
0x6 DC LDG Ctrl 2 DC Load Diagnostic Control Register 2 Go
0x7 DC LDG Ctrl 3 DC Load Diagnostic Control Register 3 Go
0x8 DC LDG Ctrl 4 DC Load Diagnostic Control Register 4 Go
0x9 DC LDG Ctrl 5 DC Load Diagnostic Control Register 5 Go
0xA DC LDG Rprt CH12 DC Load Diagnostic Report CH1, CH2 Register Go
0xB DC LDG Rprt CH34 DC Load Diagnostic Report CH3, CH4 Register Go
0xC DC LDG Rprt LO DC Load Diagnostic Report Lineout Loads Register Go
0xD Channel State Rprt CH12 Channel State Report CH1, CH2 Register Go
0xE Channel State Rprt CH34 Channel State Report CH3, CH4 Register Go
0xF Ch OC DC Fault Mem Channel Over Current and DC Detection Fault Memory Register Go
0x10 Power_Fault_Mem Power Fault Memory Register Go
0x11 Power Fault Status Power Fault Status Register Go
0x12 OTSD CS Fault Mem Temperature (OTSD) and Clock Sync Fault Memory Register Go
0x13 OTSD CS Fault Status Temperature (OTSD) and Clock Sync Fault Status Register Go
0x14 Ch Current Fault Mem Channel Load Current Fault Memory Register Go
0x15 Ch Current Warn Mem Channel Load Current Warning Memory Register Go
0x16 OTW TGFB Warn Mem Temperature (OTW) and Thermal Gain Foldback Warning Memory Register Go
0x17 OTW TGFB Warn Status Temperature (OTW) and Thermal Gain Foldback Warning Status Register Go
0x18 Ch ClipDet Warn Mem Channel Clip Detect Warning Memory Register Go
0x19 Ch ClipDet Warn Status Channel Clip Detect Warning Status Register Go
0x1C TGFB Status Thermal Gain Foldback Status Register Go
0x1D Fault Sig Conf 1 Fault Signal Configuration Register 1 Go
0x1E Fault Sig Conf 2 Fault Signal Configuration Register 2 Go
0x1F Warn Sig Conf 1 Warning Signal Configuration Register 1 Go
0x20 Warn Sig Conf 2 Warning Signal Configuration Register 2 Go
0x21 Clip Det Sig Conf Clip Detect Signal Configuration Register Go
0x22 Fault Pin Conf Fault Pin Configuration Register Go
0x23 GPIO Conf GPIO Pin Configuration Register Go
0x24 AC LDG Ctrl 1 AC Load Diagnostic Control Register 1 Go
0x25 AC LDG Ctrl 2 AC Load Diagnostic Control Register 2 Go
0x26 TWEETER DET THRESH Tweeter Detection Threshold Go
0x27 AC LDG Rprt CH1 R AC Load Diagnostic Report R CH1 Go
0x28 AC LDG Rprt CH1 I AC Load Diagnostic Report I CH1 Go
0x29 AC LDG Rprt CH2 R AC Load Diagnostic Report R CH2 Go
0x2A AC LDG Rprt CH2 I AC Load Diagnostic Report I CH2 Go
0x2B AC LDG Rprt CH3 R AC Load Diagnostic Report R CH3 Go
0x2C AC LDG Rprt CH3 I AC Load Diagnostic Report I CH3 Go
0x2D AC LDG Rprt CH4 R AC Load Diagnostic Report R CH4 Go
0x2E AC LDG Rprt CH4 I AC Load Diagnostic Report I CH Go
0x2F TWEETER DET Tweeter Detection Go
0x30 Misc Control 3 Miscellaneous Control Register 3 Go
0x32 REVID Revision ID Go
0x33 TGFB Ctrl Thermal Gain Foldback Control Register Go
0x34 AC LDG FREQ Ctrl AC Load Diagnostic Frequency Control Register Go
0x35 SYNC Ctrl Sync Pin Control Register Go
0x36 Misc Control 4 Miscellaneous Control Register 4 Go
0x37 SS Control 1 Spread Spectrum Control Register 1 Go
0x38 SS Control 2 Spread Spectrum Control Register 2 Go
0x39 PWM Phase Ctrl 1 PWM Phase Control Register 1 Go
0x3A PWM Phase Ctrl 2 PWM Phase Control Register 2 Go

7.6.1.1 Mode Control Register (Offset = 0x1) [reset = 0x00]

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Figure 7-14 Mode Control Register
7 6 5 4 3 2 1 0
RESET PWM MODE PBTL_34 PBTL_12 CH1 LO MODE CH2 LO MODE CH3 LO MODE CH4 LO MODE
W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-11 Mode Control Register Field Descriptions
Bit Field Type Reset Description
7 RESET W 0b 0: Normal Operation
1: Soft reset, will auto clear
6 PWM MODE R/W 0b 0: BD Mode
1: 1SPW Mode
5 PBTL_34 R/W 0b 0: BTL mode
1: PBTL mode of Channel 3 and Channel 4
4 PBTL_12 R/W 0b 0: BTL mode
1: PBTL mode of Channel 1 and Channel 2
3 CH1 LO MODE R/W 0b 0: Channel 1 is in normal / speaker mode
1: Channel 1 is in line output mode
2 CH2 LO MODE R/W 0b 0: Channel 2 is in normal / speaker mode
1: Channel 1 is in line output mode
1 CH3 LO MODE R/W 0b 0: Channel 3 is in normal / speaker mode
1: Channel 1 is in line output mode
0 CH4 LO MODE R/W 0b 0: Channel 4 is in normal / speaker mode
1: Channel 1 is in line output mode

7.6.1.2 Misc Control 1 Register (Offset = 0x2) [reset = 0x10]

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Figure 7-15 Misc Control 1 Register
7 6 5 4 3 2 1 0
RESERVED PI Control OTW CONTROL OC CONTROL RESERVED
R/W-0b R/W-0b R/W-1b R/W-0b R/W-0b
Table 7-12 Misc Control 1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 PI Control R/W 0b 0: Disable Pulse Injection Mode
1: Enable Pulse Injection Mode
5-4 OTW CONTROL R/W 1b 00: Global over temperature warning set to 140 °C
01: Global over temperature warning set to 130 °C
10: Global over temperature warning set to 120 °C
11:Global over temperature warning set to 110 °C
3-2 OC CONTROL R/W 0b See electrical characteristics table for details
00: OC Level 1
01: OC Level 2
10: OC Level 3
11: OC Level 4
1-0 RESERVED R/W 0b

7.6.1.3 Misc Control 2 Register (Offset = 0x3) [reset = 0xFF]

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Figure 7-16 Misc Control 2 Register
7 6 5 4 3 2 1 0
CH1 GAIN CH2 GAIN CH3 GAIN CH4 GAIN
R/W-11b R/W-11b R/W-11b R/W-11b
Table 7-13 Misc Control 2 Register Field Descriptions
Bit Field Type Reset Description
7-6 CH1 GAIN R/W 11b 00: 10dB
01: 16dB
10: 22dB
11: 28dB
5-4 CH2 GAIN R/W 11b 00: 10dB
01: 16dB
10: 22dB
11: 28dB
3-2 CH3 GAIN R/W 11b 00: 10dB
01: 16dB
10: 22dB
11: 28dB
1-0 CH4 GAIN R/W 11b 00: 10dB
01: 16dB
10: 22dB
11: 28dB

7.6.1.4 Channel State Control Register (Offset = 0x4) [reset = 0x55]

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Figure 7-17 Channel State Control Register
7 6 5 4 3 2 1 0
CH1 STATE CONTROL CH2 STATE CONTROL CH3 STATE CONTROL CH4 STATE CONTROL
R/W-1b R/W-1b R/W-1b R/W-1b
Table 7-14 Channel State Control Register Field Descriptions
Bit Field Type Reset Description
7-6 CH1 STATE CONTROL R/W 1b 00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
5-4 CH2 STATE CONTROL R/W 1b 00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
3-2 CH3 STATE CONTROL R/W 1b 00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
1-0 CH4 STATE CONTROL R/W 1b 00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic

7.6.1.5 DC LDG Ctrl 1 Register (Offset = 0x5) [reset = 0x00]

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Figure 7-18 DC LDG Ctrl 1 Register
7 6 5 4 3 2 1 0
LDG ABORT LDG BUFFER WAIT TIME RESERVED LDG WAIT BYPASS LDG SLOL DISABLE LDG BYPASS
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-15 DC LDG Ctrl 1 Register Field Descriptions
Bit Field Type Reset Description
7 LDG ABORT R/W 0b 0: Normal operation
1: Abort DC load diagnostic
6-5 LDG BUFFER WAIT TIME R/W 0b 00: Buffer wait time 1ms
01: Buffer wait time 2ms
10: Buffer wait time 5ms
11: Buffer wait time 10ms
4-3 RESERVED R/W 0b
2 LDG WAIT BYPASS R/W 0b 0: Enable the waiting loop at the end of shorted / open load detection
1: Bypass the waiting loop at the end of shorted / open load detection
1 LDG SLOL DISABLE R/W 0b 0: Shorted load and open load detection are enabled
1: Shorted load, open load and line out out detection are disabled
0 LDG BYPASS R/W 0b 0: Automatic DC diagnostic when leaving Hi-Z mode and after channel fault
1: DC diagnostic will not run automatically

7.6.1.6 DC LDG Ctrl 2 Register (Offset = 0x6) [reset = 0x00]

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Figure 7-19 DC LDG Ctrl 2 Register
7 6 5 4 3 2 1 0
RESERVED LDG S2PS2G AVG TIME LDG SLOL AVG TIME LDG LO ENABLE CH1 LDG LO ENABLE CH2 LDG LO ENABLE CH3 LDG LO ENABLE CH4
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-16 DC LDG Ctrl 2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 LDG S2PS2G AVG TIME R/W 0b Averaging time for Short-to-Power and Short-to-Ground measurement
0: 0.2 ms
1: 0.7 ms
5-4 LDG SLOL AVG TIME R/W 0b Averaging time for shorted load and open load measurements:
00: Same averaging time as selected for Short-to-Power and Short-to-Ground in bit 6 of this register
01: 10.7 ms
10: 21.3 ms
11: 42.7 ms
3 LDG LO ENABLE CH1 R/W 0b 0: Disable DC Load Diagnostics to check for line-out load on CH1
1: Enable DC Load Diagnostics to check for line-out load on CH1
2 LDG LO ENABLE CH2 R/W 0b 0: Disable DC Load Diagnostics to check for line-out load on CH2
1: Enable DC Load Diagnostics to check for line-out load on CH2
1 LDG LO ENABLE CH3 R/W 0b 0: Disable DC Load Diagnostics to check for line-out load on CH3
1: Enable DC Load Diagnostics to check for line-out load on CH3
0 LDG LO ENABLE CH4 R/W 0b 0: Disable DC Load Diagnostics to check for line-out load on CH4
1: Enable DC Load Diagnostics to check for line-out load on CH4

7.6.1.7 DC LDG Ctrl 3 Register (Offset = 0x7) [reset = 0x00]

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Figure 7-20 DC LDG Ctrl 3 Register
7 6 5 4 3 2 1 0
LDG RAMP 2 LDG SETTLING 2 LDG RAMP 1 LDG SETTLING 1
R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-17 DC LDG Ctrl 3 Register Field Descriptions
Bit Field Type Reset Description
7-6 LDG RAMP 2 R/W 0b Ramp time, shorted load and open load diagnostics
00: 15 ms
01: 30 ms
10: 10 ms
11: 20 ms
5-4 LDG SETTLING 2 R/W 0b Settling time, shorted load and open load diagnostics
00: 10 ms
01: 5 ms
10: 20 ms
11: 15 ms
3-2 LDG RAMP 1 R/W 0b Ramp time, short-to-power and short-to-ground diagnostics
00: 5 ms
01: 2.5 ms
10: 10 ms
11: 15 ms
1-0 LDG SETTLING 1 R/W 0b Settling time, short-to-power and short-to-ground diagnostics
00: 10ms
01: 5 ms
10: 20 ms
11: 30 ms

7.6.1.8 DC LDG Ctrl 4 Register (Offset = 0x8) [reset = 0x11]

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Figure 7-21 DC LDG Ctrl 4 Register
7 6 5 4 3 2 1 0
CH1 DC LDG SL CH2 DC LDG SL
R/W-1b R/W-1b
Table 7-18 DC LDG Ctrl 4 Register Field Descriptions
Bit Field Type Reset Description
7-4 CH1 DC LDG SL R/W 1b Channel 1 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3-0 CH2 DC LDG SL R/W 1b Channel 2 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω

7.6.1.9 DC LDG Ctrl 5 Register (Offset = 0x9) [reset = 0x11]

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Figure 7-22 DC LDG Ctrl 5 Register
7 6 5 4 3 2 1 0
CH3 DC LDG SL CH4 DC LDG SL
R/W-1b R/W-1b
Table 7-19 DC LDG Ctrl 5 Register Field Descriptions
Bit Field Type Reset Description
7-4 CH3 DC LDG SL R/W 1b Channel 3 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3-0 CH4 DC LDG SL R/W 1b Channel 4 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω

7.6.1.10 DC LDG Rprt CH12 Register (Offset = 0xA) [reset = 0x00]

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Figure 7-23 DC LDG Rprt CH12 Register
7 6 5 4 3 2 1 0
CH1 S2G CH1 S2P CH1 OL CH1 SL CH2 S2G CH2 S2P CH2 OL CH2 SL
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-20 DC LDG Rprt CH12 Register Field Descriptions
Bit Field Type Reset Description
7 CH1 S2G R 0b 0: No short-to-GND detected on channel 1
1: Short-to-GND detected on channel 1
6 CH1 S2P R 0b 0: No short-to-power detected on channel 1
1: Short-to-power detected on channel 1
5 CH1 OL R 0b 0: No open load detected on channel 1
1: Open load detected on channel 1
4 CH1 SL R 0b 0: No shorted load detected on channel 1
1: Shorted load detected on channel 1
3 CH2 S2G R 0b 0: No short-to-GND detected on channel 2
1: Short-to-GND detected on channel 2
2 CH2 S2P R 0b 0: No short-to-power detected on channel 2
1: Short-to-power detected on channel 2
1 CH2 OL R 0b 0: No open load detected on channel 2
1: Open load detected on channel 2
0 CH2 SL R 0b 0: No shorted load detected on channel 2
1: Shorted load detected on channel 2

7.6.1.11 DC LDG Rprt CH34 Register (Offset = 0xB) [reset = 0x00]

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Figure 7-24 DC LDG Rprt CH34 Register
7 6 5 4 3 2 1 0
CH3 S2G CH3 S2P CH3 OL CH3 SL CH4 S2G CH4 S2P CH4 OL CH4 SL
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-21 DC LDG Rprt CH34 Register Field Descriptions
Bit Field Type Reset Description
7 CH3 S2G R 0b 0: No short-to-GND detected on channel 3
1: Short-to-GND detected on channel 3
6 CH3 S2P R 0b 0: No short-to-power detected on channel 3
1: Short-to-power detected on channel 3
5 CH3 OL R 0b 0: No open load detected on channel 3
1: Open load detected on channel 3
4 CH3 SL R 0b 0: No shorted load detected on channel 3
1: Shorted load detected on channel 3
3 CH4 S2G R 0b 0: No short-to-GND detected on channel 4
1: Short-to-GND detected on channel 4
2 CH4 S2P R 0b 0: No short-to-power detected on channel 4
1: Short-to-power detected on channel 4
1 CH4 OL R 0b 0: No open load detected on channel 4
1: Open load detected on channel 4
0 CH4 SL R 0b 0: No shorted load detected on channel 4
1: Shorted load detected on channel 4

7.6.1.12 DC LDG Rprt LO Register (Offset = 0xC) [reset = 0x00]

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Figure 7-25 DC LDG Rprt LO Register
7 6 5 4 3 2 1 0
RESERVED CH1 LO LDG CH2 LO LDG CH3 LO LDG CH4 LO LDG
R-0b R-0b R-0b R-0b R-0b
Table 7-22 DC LDG Rprt LO Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 LO LDG R 0b 0: No line output detected on channel 1
1: Line output detected on channel 1
2 CH2 LO LDG R 0b 0: No line output detected on channel 2
1: Line output detected on channel 2
1 CH3 LO LDG R 0b 0: No line output detected on channel 3
1: Line output detected on channel 3
0 CH4 LO LDG R 0b 0: No line output detected on channel 4
1: Line output detected on channel 4

7.6.1.13 Channel State Rprt CH12 Register (Offset = 0xD) [reset = 0x24]

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Figure 7-26 Channel State Rprt CH12 Register
7 6 5 4 3 2 1 0
CH1 STATE REPORT CH2 STATE REPORT CH1 LDG STATE REPORT CH2 LDG STATE REPORT
R-1b R-1b R-0b R-0b
Table 7-23 Channel State Rprt CH12 Register Field Descriptions
Bit Field Type Reset Description
7-5 CH1 STATE REPORT R 1b Channel 1 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
4-2 CH2 STATE REPORT R 1b Channel 2 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
1 CH1 LDG STATE REPORT R 0b 0: DC Load Diagnostic did not complete without faults on channel 1
1: DC Load Diagnostic completed without faults on channel 1
0 CH2 LDG STATE REPORT R 0b 0: DC Load Diagnostic did not complete without faults on channel 2
1: DC Load Diagnostic completed without faults on channel 2

7.6.1.14 Channel State Rprt CH34 Register (Offset = 0xE) [reset = 0x24]

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Figure 7-27 Channel State Rprt CH34 Register
7 6 5 4 3 2 1 0
CH3 STATE REPORT CH4 STATE REPORT CH3 LDG STATE REPORT CH4 LDG STATE REPORT
R-1b R-1b R-0b R-0b
Table 7-24 Channel State Rprt CH34 Register Field Descriptions
Bit Field Type Reset Description
7-5 CH3 STATE REPORT R 1b Channel 3 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
4-2 CH4 STATE REPORT R 1b Channel 4 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
1 CH3 LDG STATE REPORT R 0b 0: DC Load Diagnostic did not complete without faults on channel 3
1: DC Load Diagnostic completed without faults on channel 3
0 CH4 LDG STATE REPORT R 0b 0: DC Load Diagnostic did not complete without faults on channel 4
1: DC Load Diagnostic completed without faults on channel 4

7.6.1.15 Ch OC DC Fault Mem Register (Offset = 0xF) [reset = 0x00]

Register clears to 0x0 upon reading.
For channel restart, DC and/or OC fault needs to be cleared by writing to register 0x30.

Return to the Summary Table.

Figure 7-28 Ch OC DC Fault Mem Register
7 6 5 4 3 2 1 0
CH1 OC FAULT STORED CH2 OC FAULT STORED CH3 OC FAULT STORED CH4 OC FAULT STORED CH1 DC FAULT STORED CH2 DC FAULT STORED CH3 DC FAULT STORED CH4 DC FAULT STORED
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-25 Ch OC DC Fault Mem Register Field Descriptions
Bit Field Type Reset Description
7 CH1 OC FAULT STORED R 0b
0: No channel 1 over current fault event stored
1: Channel 1 over current fault event stored
6 CH2 OC FAULT STORED R 0b 0: No channel 2 over current fault event stored
1: Channel 2 over current fault event stored
5 CH3 OC FAULT STORED R 0b 0: No channel 3 over current fault event stored
1: Channel 3 over current fault event stored
4 CH4 OC FAULT STORED R 0b 0: No channel 4 over current fault event stored
1: Channel 4 over current fault event stored
3 CH1 DC FAULT STORED R 0b 0: No channel 1 DC fault event stored
1: Channel 1 DC fault event stored
2 CH2 DC FAULT STORED R 0b 0: No channel 2 DC fault event stored
1: Channel 2 DC fault event stored
1 CH3 DC FAULT STORED R 0b 0: No channel 3 DC fault event stored
1: Channel 3 DC fault event stored
0 CH4 DC FAULT STORED R 0b 0: No channel 4 DC fault event stored
1: Channel 4 DC fault event stored

7.6.1.16 Power_Fault_Mem Register (Offset = 0x10) [reset = 0x00]

Register clears to 0x0 upon reading.

Return to the Summary Table.

Figure 7-29 Power_Fault_Mem Register
7 6 5 4 3 2 1 0
RESERVED GVDD FAULT STORED DVDD POR STORED PVDD OV STORED VBAT OV STORED PVDD UV STORED VBAT UV STORED
R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-26 Power_Fault_Mem Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0b
5 GVDD FAULT STORED R 0b
0: No GVDD regulator fault event stored
1: GVDD regulator fault event stored
4 DVDD POR STORED R 0b 0: No DVDD power on reset event stored
1: DVDD power on reset event stored
3 PVDD OV STORED R 0b 0: No PVDD over voltage event stored
1: PVDD over voltage event stored
2 VBAT OV STORED R 0b 0: No VBAT over voltage event stored
1: VBAT over voltage event stored
1 PVDD UV STORED R 0b 0: No PVDD under voltage event stored
1: PVDD under voltage event detected and stored
0 VBAT UV STORED R 0b 0: No VBAT under voltage event stored
1: VBAT under voltage event stored

7.6.1.17 Power Fault Status Register (Offset = 0x11) [reset = 0x00]

Return to the Summary Table.

Figure 7-30 Power Fault Status Register
7 6 5 4 3 2 1 0
GLOBAL WARNING GLOBAL FAULT GVDD FAULT RESERVED PVDD OV VBAT OV PVDD UV VBAT UV
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-27 Power Fault Status Register Field Descriptions
Bit Field Type Reset Description
7 GLOBAL WARNING R 0b 0: No warning
1: If any warning active in device, regardless of warning signal configuration
6 GLOBAL FAULT R 0b 0: No fault
1: If any fault active in device, regardless of fault signal configuration
5 GVDD FAULT R 0b 0: No GVDD regulator fault detected
1: GVDD regulator fault detected
4 RESERVED R 0b
3 PVDD OV R 0b 0: PVDD supply voltage is not above OV threshold
1: PVDD supply voltage is above OV threshold
2 VBAT OV R 0b 0: VBAT supply voltage is not above OV threshold
1: VBAT supply voltage is above OV threshold
1 PVDD UV R 0b 0: PVDD supply voltage is not below UV threshold
1:PVDD supply voltage is below UV threshold
0 VBAT UV R 0b 0: VBAT supply voltage is not below UV threshold
1: VBAT supply voltage is below UV threshold

7.6.1.18 OTSD CS Fault Mem Register (Offset = 0x12) [reset = 0x00]

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Figure 7-31 OTSD CS Fault Mem Register
7 6 5 4 3 2 1 0
RESERVED INVALID CLOCK STORED OTSD STORED CH1 OTSD STORED CH2 OTSD STORED CH3 OTSD STORED CH4 OTSD STORED
R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-28 OTSD CS Fault Mem Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0b
5 INVALID CLOCK STORED R 0b Only applies if device is configured in clock slave mode:
0: No clock synchronization fault event stored
1:Clock synchronization fault event stored
4 OTSD STORED R 0b 0: No global over temperature shutdown event stored
1:Global over temperature shutdown event stored
3 CH1 OTSD STORED R 0b 0: No channel 1 over temperature shutdown event stored
1: Channel 1 over temperature shutdown event stored
2 CH2 OTSD STORED R 0b 0: No channel 2 over temperature shutdown event stored
1: Channel 2 over temperature shutdown event stored
1 CH3 OTSD STORED R 0b 0: No channel 3 over temperature shutdown event stored
1: Channel 3 over temperature shutdown event stored
0 CH4 OTSD STORED R 0b 0: No channel 4 over temperature shutdown event stored
1: Channel 4 over temperature shutdown event stored

7.6.1.19 OTSD CS Fault Status Register (Offset = 0x13) [reset = 0x00]

Return to the Summary Table.

Figure 7-32 OTSD CS Fault Status Register
7 6 5 4 3 2 1 0
WARNING SIGNAL FAULT SIGNAL INVALID CLOCK OTSD CH1 OTSD CH2 OTSD CH3 OTSD CH4 OTSD
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-29 OTSD CS Fault Status Register Field Descriptions
Bit Field Type Reset Description
7 WARNING SIGNAL R 0b 0: If internal warning signal is not active
1: If internal warning signal is active (configured by warning signal configuration registers)
6 FAULT SIGNAL R 0b 0: If internal fault signal is not active
1: If internal fault signal is active (configured by fault signal configuration registers)
5 INVALID CLOCK R 0b Only applies if device is configured in clock slave mode:
0: No Synchronization clock error detected
1: Synchronization clock error detected
4 OTSD R 0b 0: Global die temperature is not above OTSD threshold
1: Global die temperature is above OTSD threshold
3 CH1 OTSD R 0b 0: Channel 1 temperature is not above OTSD threshold
1: Channel 1 temperature is above OTSD threshold
2 CH2 OTSD R 0b 0: Channel 2 temperature is not above OTSD threshold
1: Channel 2 temperature is above OTSD threshold
1 CH3 OTSD R 0b 0: Channel 3 temperature is not above OTSD threshold
1: Channel 3 temperature is above OTSD threshold
0 CH4 OTSD R 0b 0: Channel 4 temperature is not above OTSD threshold
1: Channel 4 temperature is above OTSD threshold

7.6.1.20 Ch Current Fault Mem Register (Offset = 0x14) [reset = 0x00]

Register clears to 0x0 upon reading.
To restart the channel, the load current faults need to be cleared by writing to Register 0x30.

Return to the Summary Table.

Figure 7-33 Ch Current Fault Mem Register
7 6 5 4 3 2 1 0
RESERVED CH1 I-LIMIT FAULT STORED CH2 I-LIMIT FAULT STORED CH3 I-LIMIT FAULT STORED CH4 I-LIMIT FAULT STORED
R-0b R-0b R-0b R-0b R-0b
Table 7-30 Ch Current Fault Mem Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 I-LIMIT FAULT STORED R 0b
0: No channel 1 load current fault event stored
1: Channel 1 load current fault event stored
2 CH2 I-LIMIT FAULT STORED R 0b 0: No channel 2 load current fault event stored
1: Channel 2 load current fault event stored
1 CH3 I-LIMIT FAULT STORED R 0b 0: No Channel 3 load current fault event stored
1: Channel 3 load current fault event stored
0 CH4 I-LIMIT FAULT STORED R 0b 0: No channel 4 load current fault event stored
1: Channel 4 load current fault event stored

7.6.1.21 Ch Current Warn Mem Register (Offset = 0x15) [reset = 0x00]

Register clears to 0x0 upon reading.

Return to the Summary Table.

Figure 7-34 Ch Current Warn Mem Register
7 6 5 4 3 2 1 0
RESERVED CH1 I-LIMIT WARN STORED CH2 I-LIMIT WARN STORED CH3 I-LIMIT WARN STORED CH4 I-LIMIT WARN STORED
R-0b R-0b R-0b R-0b R-0b
Table 7-31 Ch Current Warn Mem Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 I-LIMIT WARN STORED R 0b
0: No channel 1 load current warning event stored
1: Channel 1 load current warning event stored
2 CH2 I-LIMIT WARN STORED R 0b 0: No channel 2 load current warning event stored
1: Channel 2 load current warning event stored
1 CH3 I-LIMIT WARN STORED R 0b 0: No channel 3 load current warning event stored
1: Channel 3 load current warning event stored
0 CH4 I-LIMIT WARN STORED R 0b 0: No channel 4 load current warning event stored
1: Channel 4 load current warning event stored

7.6.1.22 OTW TGFB Warn Mem Register (Offset = 0x16) [reset = 0x00]

Register clears to 0x0 upon reading.

Return to the Summary Table.

Figure 7-35 OTW TGFB Warn Mem Register
7 6 5 4 3 2 1 0
RESERVED TGFBW STORED OTW STORED CH1 OTW STORED CH2 OTW STORED CH3 OTW STORED CH4 OTW STORED
R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-32 OTW TGFB Warn Mem Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0b
5 TGFBW STORED R 0b 0: No thermal gain fold back activation event stored
1: Thermal gain fold back activation event stored
4 OTW STORED R 0b 0: No global over temperature warning event stored
1:Global over temperature warning event stored
3 CH1 OTW STORED R 0b 0: No channel 1 over temperature warning event stored
1: Channel 1 over temperature warning event stored
2 CH2 OTW STORED R 0b 0: No channel 2 over temperature warning event stored
1: Channel 2 over temperature warning event stored
1 CH3 OTW STORED R 0b 0: No channel 3 over temperature warning event stored
1: Channel 3 over temperature warning event stored
0 CH4 OTW STORED R 0b 0: No channel 4 over temperature warning event stored
1: Channel 4 over temperature warning event stored

7.6.1.23 OTW TGFB Warn Status Register (Offset = 0x17) [reset = 0x00]

Return to the Summary Table.

Figure 7-36 OTW TGFB Warn Status Register
7 6 5 4 3 2 1 0
RESERVED TGFBW OTW CH1 OTW CH2 OTW CH3 OTW CH4 OTW
R-0b R-0b R-0b R-0b R-0b R-0b R-0b
Table 7-33 OTW TGFB Warn Status Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0b
5 TGFBW R 0b 0: Thermal gain fold back is not activated
1: Thermal gain fold back is activated
4 OTW R 0b 0: Global die temperature is not above OTW threshold
1: Global die temperature is above OTW threshold
3 CH1 OTW R 0b 0: Channel 1 temperature is not above OTW threshold
1: Channel 1 temperature is above OTW threshold
2 CH2 OTW R 0b 0: Channel 2 temperature is not above OTW threshold
1: Channel 2 temperature is above OTW threshold
1 CH3 OTW R 0b 0: Channel 3 temperature is not above OTW threshold
1: Channel 3 temperature is above OTW threshold
0 CH4 OTW R 0b 0: Channel 4 temperature is not above OTW threshold
1: Channel 4 temperature is above OTW threshold

7.6.1.24 Ch ClipDet Warn Mem Register (Offset = 0x18) [reset = 0x00]

Register clears to 0x0 upon reading.

Return to the Summary Table.

Figure 7-37 Ch ClipDet Warn Mem Register
7 6 5 4 3 2 1 0
RESERVED CH1 CLIP STORED CH2 CLIP STORED CH3 CLIP STORED CH4 CLIP STORED
R-0b R-0b R-0b R-0b R-0b
Table 7-34 Ch ClipDet Warn Mem Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 CLIP STORED R 0b 0: No channel 1 clipping event stored
1: Channel 1 clipping event stored
2 CH2 CLIP STORED R 0b 0: No channel 2 clipping event stored
1: Channel 2 clipping event stored
1 CH3 CLIP STORED R 0b 0: No channel 3 clipping event stored
1: Channel 3 clipping event stored
0 CH4 CLIP STORED R 0b 0: No channel 4 clipping event stored
1: Channel 4 clipping event stored

7.6.1.25 Ch ClipDet Warn Status Register (Offset = 0x19) [reset = 0x00]

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Figure 7-38 Ch ClipDet Warn Status Register
7 6 5 4 3 2 1 0
RESERVED CH1 CLIP CH2 CLIP CH3 CLIP CH4 CLIP
R-0b R-0b R-0b R-0b R-0b
Table 7-35 Ch ClipDet Warn Status Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 CLIP R 0b 0: Channel 1 clipping is not present or not above clip detect threshold
1: Channel 1 clipping is above clip detect threshold
2 CH2 CLIP R 0b 0: Channel 2 clipping is not present or not above clip detect threshold
1: Channel 2 clipping is above clip detect threshold
1 CH3 CLIP R 0b 0: Channel 3 clipping is not present or not above clip detect threshold
1: Channel 3 clipping is above clip detect threshold
0 CH4 CLIP R 0b 0: Channel 4 clipping is not present or not above clip detect threshold
1: Channel 4 clipping is above clip detect threshold

7.6.1.26 TGFB Status Register (Offset = 0x1C) [reset = 0x00]

Return to the Summary Table.

Figure 7-39 TGFB Status Register
7 6 5 4 3 2 1 0
RESERVED TGFB GAIN
R-0b R-0b
Table 7-36 TGFB Status Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0b
4-0 TGFB GAIN R 0b Gain set by thermal gain foldback control in response to die temperature is:
00000: 0 dB
00001: -0.5 dB
00010: -1 dB
….
10111: - 11.5 dB
11000: - 12 dB

7.6.1.27 Fault Sig Conf 1 Register (Offset = 0x1D) [reset = 0x17]

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Figure 7-40 Fault Sig Conf 1 Register
7 6 5 4 3 2 1 0
RESERVED FAULT ON PROTECTIVE SHUTDOWN FAULT ON INVALID CLOCK STORED FAULT ON OTSD STORED FAULT ON POWER FAULT STORED FAULT ON DC STORED FAULT ON OC STORED FAULT ON ILIMIT STORED
R/W-0b R/W-0b R/W-0b R/W-1b R/W-0b R/W-1b R/W-1b R/W-1b
Table 7-37 Fault Sig Conf 1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 FAULT ON PROTECTIVE SHUTDOWN R/W 0b 0: Fault signal is not activated by any CH[1..4] STATE REPORT = '101'
1: If any CH[1..4] STATE REPORT = '101', fault signal is active
5 FAULT ON INVALID CLOCK STORED R/W 0b 0: Fault signal is not activated by INVALID CLOCK STORED bit
1: If INVALID CLOCK STORED bit is set, fault signal is active
4 FAULT ON OTSD STORED R/W 1b 0: Fault signal is not activated by any CH[1..4] OTSD STORED bit or OTSD STORED bit
1: If any CH[1..4] OTSD STORED bit or OTSD STORED bit is set, fault signal is active
3 FAULT ON POWER FAULT STORED R/W 0b 0: Fault Signal is not activated by any stored bit in "Power Fault Memory Register"
1: If VBAT UV STORED bit, VBAT OV STORED bit, PVDD UV STORED bit, PVDD OV STORED bit, DVDD POR STORED bit, or GVDD FAULT STORED bit is set, fault signal is active.
2 FAULT ON DC STORED R/W 1b 0: Fault signal is not activated by any CH[1..4] DC FAULT STORED bit
1: If any CH[1..4] DC FAULT STORED bit is set, fault signal is active
1 FAULT ON OC STORED R/W 1b 0: Fault signal is not activated by any CH[1..4] OC FAULT STORED bit
1: If any CH[1..4] OC FAULT STORED bit is set, fault signal is active
0 FAULT ON ILIMIT STORED R/W 1b 0: Fault signal is not activated by any CH[1..4] I-LIMIT FAULT STORED bit
1: If any CH[1..4] I-LIMIT FAULT STORED bit is set, fault signal is active

7.6.1.28 Fault Sig Conf 2 Register (Offset = 0x1E) [reset = 0x00]

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Figure 7-41 Fault Sig Conf 2 Register
7 6 5 4 3 2 1 0
RESERVED FAULT ON WARN FAULT ON INVALID CLOCK FAULT ON OTSD FAULT ON POWER FAULT RESERVED RESERVED FAULT ON INCOMPLETE LDG
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-38 Fault Sig Conf 2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 FAULT ON WARN R/W 0b 0: Fault signal is not activated when warning singal is active.
1: Fault signal is active when warning signal is active
5 FAULT ON INVALID CLOCK R/W 0b 0: Fault signal is not activated by INVALID CLOCK bit
1: If INVALID CLOCK bit is set, fault signal is active
4 FAULT ON OTSD R/W 0b 0: Fault signal is not activated by any CH[1..4] OTSD bit or OTSD
1: If any CH[1..4] OTSD bit or OTSD bit is set, fault signal is active
3 FAULT ON POWER FAULT R/W 0b 0: Fault Signal is not activated by any stored bit in "Power Fault Status Register"
1: If VBAT UV bit, VBAT OV bit, PVDD UV bit, PVDD OV bit, or GVDD FAULT bit is set, fault signal is active.
2 RESERVED R/W 0b
1 RESERVED R/W 0b
0 FAULT ON INCOMPLETE LDG R/W 0b 0: Fault signal is not activated by any CH[1..4] LDG STATE REPORT bit
1: If any CH[1..4] LDG STATE REPORT bit is not set, fault signal Is active

7.6.1.29 Warn Sig Conf 1 Register (Offset = 0x1F) [reset = 0x04]

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Figure 7-42 Warn Sig Conf 1 Register
7 6 5 4 3 2 1 0
RESERVED WARN ON CLIP DET STORED WARN ON INVALID CLOCK STORED WARN ON OTSD STORED WARN ON POWER FAULT STORED WARN ON OTW STORED WARN ON TGFB STORED WARN ON ILIMIT STORED
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b R/W-0b R/W-0b
Table 7-39 Warn Sig Conf 1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 WARN ON CLIP DET STORED R/W 0b 0: Warning signal is not activated by any CH[1..4] CLIP STORED bit
1: If any CH[1..4] CLIP STORED bit is set, warning signal is active
5 WARN ON INVALID CLOCK STORED R/W 0b 0: Warning signal is not activated by INVALID CLOCK STORED bit
1: If INVALID CLOCK STORED bit is set, warning signal is active
4 WARN ON OTSD STORED R/W 0b 0: Warning signal is not activated by any CH[1..4] OTSD STORED bit or OTSD STORED
1: If any CH[1..4] OTSD STORED bit or OTSD STORED bit is set, warning signal is active
3 WARN ON POWER FAULT STORED R/W 0b 0: Warning Signal is not activated by any stored bit in "Power Fault Memory Register"
1: If VBAT UV STORED bit, VBAT OV STORED bit, PVDD UV STORED bit, PVDD OV STORED bit, DVDD POR STORED bit, or GVDD FAULT STORED bit is set, warning signal is active.
2 WARN ON OTW STORED R/W 1b 0: Warning signal is not activated by any CH[1..4] OTW STORED bit or OTW STORED bit
1: If any CH[1..4] OTW STORED bit or OTW STORED bit is set, warning signal is active
1 WARN ON TGFB STORED R/W 0b 0: Warning signal is not activated by TGFBW STORED
1: Warning signal is active if TGFBW STORED is active
0 WARN ON ILIMIT STORED R/W 0b 0: Warning signal is not activated by any CH[1..4] I-LIMIT WARN STORED bit
1: If any CH[1..4] I-LIMIT WARN STORED bit is set, warning signal is active

7.6.1.30 Warn Sig Conf 2 Register (Offset = 0x20) [reset = 0x00]

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Figure 7-43 Warn Sig Conf 2 Register
7 6 5 4 3 2 1 0
RESERVED WARN ON INVALID CLOCK WARN ON OTSD WARN ON POWER FAULT WARN ON OTW WARN ON TGFB WARN ON INCOMPLETE LDG
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-40 Warn Sig Conf 2 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0b
5 WARN ON INVALID CLOCK R/W 0b 0: Warning signal is not activated by INVALID CLOCK bit
1: If INVALID CLOCK bit is set, warning signal is active
4 WARN ON OTSD R/W 0b 0: Warning signal is not activated by any CH[1..4] OTSD bit or OTSD
1: If any CH[1..4] OTSD bit or OTSD bit is set, warning signal is active
3 WARN ON POWER FAULT R/W 0b 0: Warning Signal is not activated by any stored bit in "Power Fault Status Register"
1: If VBAT UV bit, VBAT OV bit, PVDD UV bit, PVDD OV bit, or GVDD FAULT bit is set, warning signal is active.
2 WARN ON OTW R/W 0b 0: Warning signal is not activated by any CH[1..4] OTW bit or OTW bit
1: If any CH[1..4] OTW STORED bit or OTW STORED bit is set, warning signal is active
1 WARN ON TGFB R/W 0b 0: Warning signal is not activated by TGFBW
1: Warning signal is active if TGFBW is active
0 WARN ON INCOMPLETE LDG R/W 0b 0: Warning signal is not activated by any CH[1..4] LDG STATE REPORT bit
1: If any CH[1..4] LDG STATE REPORT bit is not set, warning signal is active

7.6.1.31 Clip Det Sig Conf Register (Offset = 0x21) [reset = 0x00]

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Figure 7-44 Clip Det Sig Conf Register
7 6 5 4 3 2 1 0
RESERVED CLIP DET EN CLIP DET LVL CLIP DET CH34 GRP2 CLIP DET CH34 GRP1 CLIP DET CH12 GRP2 CLIP DET CH12 GRP1
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-41 Clip Det Sig Conf Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 CLIP DET EN R/W 0b 0: Clip detect is disabled
1: Clip detect is enabled
5-4 CLIP DET LVL R/W 0b 00: 2% THD
01: 5% THD
10: 10% THD
11: 1% THD
3 CLIP DET CH34 GRP2 R/W 0b 0: Clip Detect Signal Group 2 is not activated by CH3 CLIP or CH4 CLIP
1: Clip Detect Signal Group 2 is active when CH3 CLIP or CH4 CLIP is active
2 CLIP DET CH34 GRP1 R/W 0b 0: Clip Detect Signal Group 1 is not activated by CH3 CLIP or CH4 CLIP
1: Clip Detect Signal Group 1 is active when CH3 CLIP or CH4 CLIP is active
1 CLIP DET CH12 GRP2 R/W 0b 0: Clip Detect Signal Group 2 is not activated by CH1 CLIP or CH2 CLIP
1: Clip Detect Signal Group 2 is active when CH1 CLIP or CH2 CLIP is active
0 CLIP DET CH12 GRP1 R/W 0b 0: Clip Detect Signal Group 1 is not activated by CH1 CLIP or CH2 CLIP
1: Clip Detect Signal Group 1 is active when CH1 CLIP or CH2 CLIP is active

7.6.1.32 Fault Pin Conf Register (Offset = 0x22) [reset = 0x00]

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Figure 7-45 Fault Pin Conf Register
7 6 5 4 3 2 1 0
RESERVED FAULT PIN CONF
R/W-0b R/W-0b
Table 7-42 Fault Pin Conf Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0b
3-0 FAULT PIN CONF R/W 0b Fault Pin is set to:
0000: FaultZ
Open Drain Output. Active low when fault signal is active.
0001: WarningZ - Open Drain Output. Active low when warning signal is active.
0010: Clip Detect 1 - Buffer Output. Active high when clip detect group 1 signal is active.
0011: Clip Detect 2 - Buffer Output. Active high when clip detect group 2 signal is active.

7.6.1.33 GPIO Conf Register (Offset = 0x23) [reset = 0x00]

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Figure 7-46 GPIO Conf Register
7 6 5 4 3 2 1 0
GPIO2 PIN CONF GPIO1 PIN CONF
R/W-0b R/W-0b
Table 7-43 GPIO Conf Register Field Descriptions
Bit Field Type Reset Description
7-4 GPIO2 PIN CONF R/W 0b GPIO 2 pin set to:
0000: Hi-Z
0001: WarningZ Pin - Open Drain Output. Active low when warning signal is active.
0010: FaultZ Pin - Open Drain Output. Active low when fault signal is active.
0011: Clip Detect 1 - Buffer Output. Active high when clip detect group 1 signal is active.
0100: Clip Detect 2 - Buffer Output. Active high when clip detect group 2 signal is active.
0101: Sync out - Buffer Output. Sends output stage switching frequency
0110: DVDD (high)
0111: GND (low)
1000: Sync in - Input. Accepts switching frequency of clock master device
1001: MuteZ - Input. Low level input will mute the device
3-0 GPIO1 PIN CONF R/W 0b GPIO 1 pin set to:
0000: Hi-Z
0001: WarningZ - Open Drain Output. Active low when warning signal is active.
0010: FaultZ - Open Drain Output. Active low when fault signal is active.
0011: Clip Detect 1 - Buffer Output. Active high when clip detect group 1 signal is active.
0100: Clip Detect 2 - Buffer Output. Active high when clip detect group 2 signal is active.
0101: Sync out - Buffer Output. Sends output stage switching frequency
0110: DVDD (high)
0111: GND (low)
1000: Sync in - Input. Accepts switching frequency of clock master device
1001: MuteZ - Input. Low level input will mute the device

7.6.1.34 AC LDG Ctrl 1 Register (Offset = 0x24) [reset = 0x00]

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Figure 7-47 AC LDG Ctrl 1 Register
7 6 5 4 3 2 1 0
RESERVED AC DIAG GAIN CH1 AC DIAG START CH2 AC DIAG START CH3 AC DIAG START CH4 AC DIAG START
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-44 AC LDG Ctrl 1 Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 0b
4 AC DIAG GAIN R/W 0b 0: Gain 1 (0-100 Ω)
1: Gain 8 (0-12.5 Ω)
3 CH1 AC DIAG START R/W 0b 0: Normal operation
1: Start AC diagnostic on channel 1 once channel is in Hi-Z mode
2 CH2 AC DIAG START R/W 0b 0: Normal operation
1: Start AC diagnostic on channel 2 once channel is in Hi-Z mode
1 CH3 AC DIAG START R/W 0b 0: Normal operation
1: Start AC diagnostic on channel 3 once channel is in Hi-Z mode
0 CH4 AC DIAG START R/W 0b 0: Normal operation
1: Start AC diagnostic on channel 4 once channel is in Hi-Z mode

7.6.1.35 AC LDG Ctrl 2 Register (Offset = 0x25) [reset = 0x8]

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Figure 7-48 AC LDG Ctrl 2 Register
7 6 5 4 3 2 1 0
RESERVED TW DET AVG RESERVED TW DET CALC TYPE TW DET JUDGE
R/W-0b R/W-1b R/W-0b R/W-0b R/W-0b
Table 7-45 AC LDG Ctrl 2 Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0b
3 TW DET AVG R/W 1b 0: Fast mode
1: Normal mode
2 RESERVED R/W 0b
1 TW DET CALC TYPE R/W 0b 0: AC pass/fail judgement type 2
Calculate magnitude of impedance as Re(Z)+0.5*Im(Z)
1: AC pass/fail judgement type 1
Calculate magnitude of impedance as Re(Z)
0 TW DET JUDGE R/W 0b 0: Enable Tweeter detection judegement
Calculate magnitude of impedance
Check whether calculated result is lower than tweeter detection threshold value
If yes, set tweeter detection bit
1: Disable Tweeter detection calculation

7.6.1.36 TWEETER DET THRESH Register (Offset = 0x26) [reset = 0x00]

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Figure 7-49 TWEETER DET THRESH Register
7 6 5 4 3 2 1 0
TW DET THRESHOLD
R/W-0b
Table 7-46 TWEETER DET THRESH Register Field Descriptions
Bit Field Type Reset Description
7-0 TW DET THRESHOLD R/W 0b Set the reference value for AC load diag pass/fail judgement.
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.37 AC LDG Rprt CH1 R Register (Offset = 0x27) [reset = 0x00]

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Figure 7-50 AC LDG Rprt CH1 R Register
7 6 5 4 3 2 1 0
CH1 AC IMP R
R-0b
Table 7-47 AC LDG Rprt CH1 R Register Field Descriptions
Bit Field Type Reset Description
7-0 CH1 AC IMP R R 0b Register value corresponds to the real part of complex impedance seen at CH1 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.38 AC LDG Rprt CH1 I Register (Offset = 0x28) [reset = 0x00]

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Figure 7-51 AC LDG Rprt CH1 I Register
7 6 5 4 3 2 1 0
CH1 AC IMP I
R-0b
Table 7-48 AC LDG Rprt CH1 I Register Field Descriptions
Bit Field Type Reset Description
7-0 CH1 AC IMP I R 0b Register value corresponds to the complement of the imaginary part of complex impedance seen at CH1 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.39 AC LDG Rprt CH2 R Register (Offset = 0x29) [reset = 0x00]

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Figure 7-52 AC LDG Rprt CH2 R Register
7 6 5 4 3 2 1 0
CH2 AC IMP R
R-0b
Table 7-49 AC LDG Rprt CH2 R Register Field Descriptions
Bit Field Type Reset Description
7-0 CH2 AC IMP R R 0b Register value corresponds to the real part of complex impedance seen at CH2 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.40 AC LDG Rprt CH2 I Register (Offset = 0x2A) [reset = 0x00]

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Figure 7-53 AC LDG Rprt CH2 I Register
7 6 5 4 3 2 1 0
CH2 AC IMP I
R-0b
Table 7-50 AC LDG Rprt CH2 I Register Field Descriptions
Bit Field Type Reset Description
7-0 CH2 AC IMP I R 0b Register value corresponds to the complement of the imaginary part of complex impedance seen at CH2 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.41 AC LDG Rprt CH3 R Register (Offset = 0x2B) [reset = 0x00]

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Figure 7-54 AC LDG Rprt CH3 R Register
7 6 5 4 3 2 1 0
CH3 AC IMP R
R-0b
Table 7-51 AC LDG Rprt CH3 R Register Field Descriptions
Bit Field Type Reset Description
7-0 CH3 AC IMP R R 0b Register value corresponds to the real part of complex impedance seen at CH3 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.42 AC LDG Rprt CH3 I Register (Offset = 0x2C) [reset = 0x00]

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Figure 7-55 AC LDG Rprt CH3 I Register
7 6 5 4 3 2 1 0
CH3 AC IMP I
R-0b
Table 7-52 AC LDG Rprt CH3 I Register Field Descriptions
Bit Field Type Reset Description
7-0 CH3 AC IMP I R 0b Register value corresponds to the complement of the imaginary part of complex impedance seen at CH3 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.43 AC LDG Rprt CH4 R Register (Offset = 0x2D) [reset = 0x00]

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Figure 7-56 AC LDG Rprt CH4 R Register
7 6 5 4 3 2 1 0
CH4 AC IMP R
R-0b
Table 7-53 AC LDG Rprt CH4 R Register Field Descriptions
Bit Field Type Reset Description
7-0 CH4 AC IMP R R 0b Register value corresponds to the real part of complex impedance seen at CH4 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.44 AC LDG Rprt CH4 I Register (Offset = 0x2E) [reset = 0x00]

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Figure 7-57 AC LDG Rprt CH4 I Register
7 6 5 4 3 2 1 0
CH4 AC IMP I
R-0b
Table 7-54 AC LDG Rprt CH4 I Register Field Descriptions
Bit Field Type Reset Description
7-0 CH4 AC IMP I R 0b Register value corresponds to the complement of the imaginary part of complex impedance seen at CH4 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See Section 7.6.1.34

7.6.1.45 TWEETER DET Register (Offset = 0x2F) [reset = 0x00]

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Figure 7-58 TWEETER DET Register
7 6 5 4 3 2 1 0
RESERVED CH1 TW DET CH2 TW DET CH3 TW DET CH4 TWDET
R-0b R-0b R-0b R-0b R-0b
Table 7-55 TWEETER DET Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0b
3 CH1 TW DET R 0b 0: No tweeter detected on channel 1.
1: Tweeter detected on channel 1.
2 CH2 TW DET R 0b 0: No tweeter detected on channel 2.
1: Tweeter detected on channel 2.
1 CH3 TW DET R 0b 0: No tweeter detected on channel 3.
1: Tweeter detected on channel 3.
0 CH4 TW DET R 0b 0: No tweeter detected on channel 4.
1: Tweeter detected on channel 4.

7.6.1.46 Misc Control 3 Register (Offset = 0x30) [reset = 0x00]

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Figure 7-59 Misc Control 3 Register
7 6 5 4 3 2 1 0
CLEAR FAULT RESERVED PRECHG TIME OTSD AUTO RECOVERY RESERVED PULL UP RESERVED
W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-56 Misc Control 3 Register Field Descriptions
Bit Field Type Reset Description
7 CLEAR FAULT W 0b 0: Normal operation
1: Clear fault
6 RESERVED R/W 0b
5-4 PRECHG TIME R/W 0b Precharge wait time sets the time for AC coupling input caps to settle during startup
0: 20 ms
1: 15 ms
2: 40 ms
3: 50 ms
3 OTSD AUTO RECOVERY R/W 0b 0: Device will not auto recover from over temperature shutdown
1: Device will auto recover from over temperature shutdown
2 RESERVED R/W 0b
1 PULL UP R/W 0b Control internal pull-up for GPIO1 and GPIO2 if configured to Open Drain Output
0: Enable internal pull-up
1: Disable internal pull-up
0 RESERVED R/W 0b

7.6.1.47 REVID Register (Offset = 0x32) [reset = 0x00]

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Figure 7-60 REVID Register
7 6 5 4 3 2 1 0
REV ID
R-0b
Table 7-57 REVID Register Field Descriptions
Bit Field Type Reset Description
7-0 REV ID R

0x21

 Revision ID

7.6.1.48 TGFB Ctrl Register (Offset = 0x33) [reset = 0x00]

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Figure 7-61 TGFB Ctrl Register
7 6 5 4 3 2 1 0
ZC WAIT TIME BYPASS ZC BYPASS ATTACK RELEASE
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-58 TGFB Ctrl Register Field Descriptions
Bit Field Type Reset Description
7-6 ZC WAIT TIME R/W 0b System waits this period for zero crossing, then changes gain regardless.
00: 20 µs
01: 80 µs
10: 320 µs
11: 1280 µs
5 BYPASS R/W 0b 0: Enable Thermal Gain Foldback
1: Disable Thermal Gain Foldback
4 ZC BYPASS R/W 0b 0: Enable zero crossing detection
1: Disable zero crossing detection. Gain changes as soon as thermal condition is met without waiting for zero detection.
3-2 ATTACK R/W 0b 00: 1 dB / 100ms
01: 1 dB / 200ms
10: 1 dB / 400ms
11: 1 dB / 800ms
1-0 RELEASE R/W 0b 00: 1 dB / 200ms
01: 1 dB / 400ms
10: 1 dB / 800ms
11: 1 dB / 1600ms

7.6.1.49 AC LDG FREQ Ctrl Register (Offset = 0x34) [reset = 0xC8]

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Figure 7-62 AC LDG FREQ Ctrl Register
7 6 5 4 3 2 1 0
STIMULUS FREQUENCY (93.75 Hz/bit)
R/W-11001000b
Table 7-59 AC LDG FREQ Ctrl Register Field Descriptions
Bit Field Type Reset Description
7-0 STIMULUS FREQUENCY (93.75 Hz/bit) R/W 11001000b 0000 0000: Default. 18.75kHz
0000 0001: 93.75 Hz
0000 0010: 187.5 Hz
….
1100 1000: 18.75 kHz
….
1111 1111: 23.90625 kHz

7.6.1.50 SYNC Ctrl Register (Offset = 0x35) [reset = 0x1]

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Figure 7-63 SYNC Ctrl Register
7 6 5 4 3 2 1 0
RESERVED SYNC ERROR WD SYNC ERROR DET BYPASS MASTER SLAVE
R/W-0b R/W-0b R/W-0b R/W-1b
Table 7-60 SYNC Ctrl Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0b
3-2 SYNC ERROR WD R/W 0b SYNC Clock Error watchdog timer.
For PWM frequency of 2.1MHz or 2.3MHz, timer set to
00: 2.5µs
01: 5µs
10: 7.5µs
11: 10µs

For PWM frequency of 384kHz, 460kHz or 576kHz, timer set to
00: 5µs
01: 10µs
10: 15µs
11: 20µs
1 SYNC ERROR DET BYPASS R/W 0b 0: SYNC Clock Error detection
1: Clock Error Detection bypassed
0 MASTER SLAVE R/W 1b 0: Slave Mode - GPIO 1 or 2 need to be configured as SYNC IN and external clock required
1: Master Mode - Device generates clock internally

7.6.1.51 Misc Control 4 Register (Offset = 0x36) [reset = 0x00]

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Figure 7-64 Misc Control 4 Register
7 6 5 4 3 2 1 0
RESERVED TLSBY SSC4 SPREAD SPECTRUM SYNC CLOCK PWM FREQUENCY
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-61 Misc Control 4 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6 TLSBY R/W 0b Three level mode for standby pin
0: Two level mode
1: Three level mode with MUTE at mid-voltage level
5-4 SSC4 R/W 0b Spread Spectrum Control 4
3 SPREAD SPECTRUM SYNC CLOCK R/W 0b Select whether sync clock input will be spread spectrum modulated before setting PWM frequency. Applies if device is set to clock slave mode.
0: Spread spectrum mode applied to clock sync input signal
1: Spread spectrum mode not applied to clock sync input signal
2-0 PWM FREQUENCY R/W 0b PWM switching frequency setting:
000: 2.1 MHz
001: 2.3 MHz
010: 576 kHz
011: 384 kHz
100: 460 kHz

7.6.1.52 SS Control 1 Register (Offset = 0x37) [reset = 0x22]

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Figure 7-65 SS Control 1 Register
7 6 5 4 3 2 1 0
SSC1
R/W-100010b
Table 7-62 SS Control 1 Register Field Descriptions
Bit Field Type Reset Description
7-0 SSC1 R/W 100010b Spread Spectrum Control 1

7.6.1.53 SS Control 2 Register (Offset = 0x38) [reset = 0x80]

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Figure 7-66 SS Control 2 Register
7 6 5 4 3 2 1 0
SS ENABLE RESERVED SSC3 SSC2
R/W-1b R/W-0b R/W-0b R/W-0b
Table 7-63 SS Control 2 Register Field Descriptions
Bit Field Type Reset Description
7 SS ENABLE R/W 1b 0: Disable spread spectrum mode
1: Enable spread spectrum mode
6 RESERVED R/W 0b
5-4 SSC3 R/W 0b Spread Spectrum Control 3
3-0 SSC2 R/W 0b Spread Spectrum Control 2

7.6.1.54 PWM Phase Ctrl 1 Register (Offset = 0x39) [reset = 0x40]

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Figure 7-67 PWM Phase Ctrl 1 Register
7 6 5 4 3 2 1 0
RESERVED PHASE CH2 RESERVED PHASE SEL
R/W-0b R/W-100b R/W-0b R/W-0b
Table 7-64 PWM Phase Ctrl 1 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6-4 PHASE CH2 R/W 100b Phase offset of Channel 2 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree
3-1 RESERVED R/W 0b
0 PHASE SEL R/W 0b Adjustment mode for PWM phase of channel 2, 3 and 4 relative to channel 1
0: Manual mode
1: Automatic mode

7.6.1.55 PWM Phase Ctrl 2 Register (Offset = 0x3A) [reset = 0x62]

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Figure 7-68 PWM Phase Ctrl 2 Register
7 6 5 4 3 2 1 0
RESERVED PHASE CH4 RESERVED PHASE CH3
R/W-0b R/W-110b R/W-0b R/W-10b
Table 7-65 PWM Phase Ctrl 2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b
6-4 PHASE CH4 R/W 110b Phase offset of Channel 4 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree
3 RESERVED R/W 0b
2-0 PHASE CH3 R/W 10b Phase offset of Channel 3 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree