ZHCSDR5B March   2012  – April 2015 TMS320C6654

PRODUCTION DATA.  

  1. 1 C6654 特性和描述
    1. 1.1 特性
    2. 1.2 KeyStone 架构
    3. 1.3 器件描述
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 DSP Core Description
    3. 3.3 Memory Map Summary
    4. 3.4 Boot Sequence
    5. 3.5 Boot Modes Supported and PLL Settings
      1. 3.5.1 Boot Device Field
      2. 3.5.2 Device Configuration Field
        1. 3.5.2.1 EMIF16 / UART / No Boot Device Configuration
          1. 3.5.2.1.1 No Boot Mode
          2. 3.5.2.1.2 UART Boot Mode
          3. 3.5.2.1.3 EMIF16 Boot Mode
        2. 3.5.2.2 Ethernet (SGMII) Boot Device Configuration
        3. 3.5.2.3 NAND Boot Device Configuration
        4. 3.5.2.4 PCI Boot Device Configuration
        5. 3.5.2.5 I2C Boot Device Configuration
          1. 3.5.2.5.1 I2C Master Mode
          2. 3.5.2.5.2 I2C Passive Mode
        6. 3.5.2.6 SPI Boot Device Configuration
      3. 3.5.3 Boot Parameter Table
        1. 3.5.3.1 Sleep / XIP Mode Parameter Table
        2. 3.5.3.2 SRIO Mode Boot Parameter Table
        3. 3.5.3.3 Ethernet Mode Boot Parameter Table
        4. 3.5.3.4 NAND Mode Boot Parameter Table
        5. 3.5.3.5 PCIE Mode Boot Parameter Table
        6. 3.5.3.6 I2C Mode Boot Parameter Table
        7. 3.5.3.7 SPI Mode Boot Parameter Table
        8. 3.5.3.8 Hyperlink Mode Boot Parameter Table
        9. 3.5.3.9 UART Mode Boot Parameter Table
    6. 3.6 PLL Boot Configuration Settings
    7. 3.7 Second-Level Bootloaders
    8. 3.8 Terminals
      1. 3.8.1 Package Terminals
      2. 3.8.2 Pin Map
    9. 3.9 Terminal Functions
  4. 4 Device Configuration
    1. 4.1 Device Configuration at Device Reset
    2. 4.2 Peripheral Selection After Device Reset
    3. 4.3 Device State Control Registers
      1. 4.3.1  Device Status Register
      2. 4.3.2  Device Configuration Register
      3. 4.3.3  JTAG ID (JTAGID) Register Description
      4. 4.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 4.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
      6. 4.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
      7. 4.3.7  Reset Status (RESET_STAT) Register
      8. 4.3.8  Reset Status Clear (RESET_STAT_CLR) Register
      9. 4.3.9  Boot Complete (BOOTCOMPLETE) Register
      10. 4.3.10 Power State Control (PWRSTATECTL) Register
      11. 4.3.11 NMI Event Generation to CorePac (NMIGRx) Register
      12. 4.3.12 IPC Generation (IPCGRx) Registers
      13. 4.3.13 IPC Acknowledgement (IPCARx) Registers
      14. 4.3.14 IPC Generation Host (IPCGRH) Register
      15. 4.3.15 IPC Acknowledgement Host (IPCARH) Register
      16. 4.3.16 Timer Input Selection Register (TINPSEL)
      17. 4.3.17 Timer Output Selection Register (TOUTPSEL)
      18. 4.3.18 Reset Mux (RSTMUXx) Register
      19. 4.3.19 Device Speed (DEVSPEED) Register
      20. 4.3.20 Pin Control 0 (PIN_CONTROL_0) Register
      21. 4.3.21 Pin Control 1 (PIN_CONTROL_1) Register
      22. 4.3.22 uPP Clock Source (UPP_CLOCK) Register
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 System Interconnect
    1. 5.1 Internal Buses and Switch Fabrics
    2. 5.2 Switch Fabric Connections Matrix
    3. 5.3 TeraNet Switch Fabric Connections
    4. 5.4 Bus Priorities
      1. 5.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
      2. 5.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
  6. 6 C66x CorePac
    1. 6.1 Memory Architecture
      1. 6.1.1 L1P Memory
      2. 6.1.2 L1D Memory
      3. 6.1.3 L2 Memory
      4. 6.1.4 MSM Controller
      5. 6.1.5 L3 Memory
    2. 6.2 Memory Protection
    3. 6.3 Bandwidth Management
    4. 6.4 Power-Down Control
    5. 6.5 C66x CorePac Revision
    6. 6.6 C66x CorePac Register Descriptions
  7. 7 Device Operating Conditions
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrical Characteristics
    4. 7.4 Power Supply to Peripheral I/O Mapping
  8. 8 Peripheral Information and Electrical Specifications
    1. 8.1  Recommended Clock and Control Signal Transition Behavior
    2. 8.2  Power Supplies
      1. 8.2.1 Power-Supply Sequencing
        1. 8.2.1.1 Core-Before-IO Power Sequencing
        2. 8.2.1.2 IO-Before-Core Power Sequencing
        3. 8.2.1.3 Prolonged Resets
        4. 8.2.1.4 Clocking During Power Sequencing
      2. 8.2.2 Power-Down Sequence
      3. 8.2.3 Power Supply Decoupling and Bulk Capacitors
      4. 8.2.4 SmartReflex
    3. 8.3  Power Sleep Controller (PSC)
      1. 8.3.1 Power Domains
      2. 8.3.2 Clock Domains
      3. 8.3.3 PSC Register Memory Map
    4. 8.4  Reset Controller
      1. 8.4.1 Power-on Reset
      2. 8.4.2 Hard Reset
      3. 8.4.3 Soft Reset
      4. 8.4.4 Local Reset
      5. 8.4.5 Reset Priority
      6. 8.4.6 Reset Controller Register
      7. 8.4.7 Reset Electrical Data / Timing
    5. 8.5  Main PLL and PLL Controller
      1. 8.5.1 Main PLL Controller Device-Specific Information
        1. 8.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 8.5.1.2 Main PLL Controller Operating Modes
        3. 8.5.1.3 Main PLL Stabilization, Lock, and Reset Times
      2. 8.5.2 PLL Controller Memory Map
        1. 8.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 8.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
        3. 8.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 8.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 8.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 8.5.2.6 Reset Type Status Register (RSTYPE)
        7. 8.5.2.7 Reset Control Register (RSTCTRL)
        8. 8.5.2.8 Reset Configuration Register (RSTCFG)
        9. 8.5.2.9 Reset Isolation Register (RSISO)
      3. 8.5.3 Main PLL Control Register
      4. 8.5.4 Main PLL and PLL Controller Initialization Sequence
      5. 8.5.5 Main PLL Controller/PCIe Clock Input Electrical Data/Timing
    6. 8.6  DDR3 PLL
      1. 8.6.1 DDR3 PLL Control Register
      2. 8.6.2 DDR3 PLL Device-Specific Information
      3. 8.6.3 DDR3 PLL Initialization Sequence
      4. 8.6.4 DDR3 PLL Input Clock Electrical Data/Timing
    7. 8.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 8.7.1 EDMA3 Device-Specific Information
      2. 8.7.2 EDMA3 Channel Controller Configuration
      3. 8.7.3 EDMA3 Transfer Controller Configuration
      4. 8.7.4 EDMA3 Channel Synchronization Events
    8. 8.8  Interrupts
      1. 8.8.1 Interrupt Sources and Interrupt Controller
      2. 8.8.2 CIC Registers
        1. 8.8.2.1 CIC0 Register Map
        2. 8.8.2.2 CIC1 Register Map
      3. 8.8.3 Inter-Processor Register Map
      4. 8.8.4 NMI and LRESET
      5. 8.8.5 External Interrupts Electrical Data/Timing
    9. 8.9  Memory Protection Unit (MPU)
      1. 8.9.1 MPU Registers
        1. 8.9.1.1 MPU Register Map
        2. 8.9.1.2 Device-Specific MPU Registers
          1. 8.9.1.2.1 Configuration Register (CONFIG)
      2. 8.9.2 MPU Programmable Range Registers
        1. 8.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
        3. 8.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
        4. 8.9.2.4 MPU Registers Reset Values
    10. 8.10 DDR3 Memory Controller
      1. 8.10.1 DDR3 Memory Controller Device-Specific Information
      2. 8.10.2 DDR3 Memory Controller Electrical Data/Timing
    11. 8.11 I2C Peripheral
      1. 8.11.1 I2C Device-Specific Information
      2. 8.11.2 I2C Peripheral Register Description(s)
      3. 8.11.3 I2C Electrical Data/Timing
        1. 8.11.3.1 Inter-Integrated Circuits (I2C) Timing
    12. 8.12 SPI Peripheral
      1. 8.12.1 SPI Electrical Data/Timing
        1. 8.12.1.1 SPI Timing
    13. 8.13 UART Peripheral
    14. 8.14 PCIe Peripheral
    15. 8.15 EMIF16 Peripheral
      1. 8.15.1 EMIF16 Electrical Data/Timing
    16. 8.16 Ethernet Media Access Controller (EMAC)
      1. 8.16.1 EMAC Device-Specific Information
      2. 8.16.2 EMAC Peripheral Register Description(s)
      3. 8.16.3 EMAC Electrical Data/Timing (SGMII)
    17. 8.17 Management Data Input/Output (MDIO)
      1. 8.17.1 MDIO Peripheral Registers
      2. 8.17.2 MDIO Timing
    18. 8.18 Timers
      1. 8.18.1 Timers Device-Specific Information
      2. 8.18.2 Timers Electrical Data/Timing
    19. 8.19 General-Purpose Input/Output (GPIO)
      1. 8.19.1 GPIO Device-Specific Information
      2. 8.19.2 GPIO Electrical Data/Timing
    20. 8.20 Semaphore2
    21. 8.21 Multichannel Buffered Serial Port (McBSP)
      1. 8.21.1 McBSP Peripheral Register
      2. 8.21.2 McBSP Electrical Data/Timing
        1. 8.21.2.1 McBSP Timing
    22. 8.22 Universal Parallel Port (uPP)
      1. 8.22.1 uPP Register Descriptions
    23. 8.23 Emulation Features and Capability
      1. 8.23.1 Advanced Event Triggering (AET)
      2. 8.23.2 Trace
        1. 8.23.2.1 Trace Electrical Data/Timing
      3. 8.23.3 IEEE 1149.1 JTAG
        1. 8.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 8.23.3.2 JTAG Electrical Data/Timing
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device and Development-Support Tool Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Links
      2. 9.2.2 社区资源
    3. 9.3 商标
    4. 9.4 静电放电警告
    5. 9.5 Glossary
  10. 10Mechanical Data
    1. 10.1 Thermal Data
    2. 10.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • CZH|625
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Device Configuration

On the C6654 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.

4.1 Device Configuration at Device Reset

Table 4-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP can be taken out of reset.

Also, please note that most of the device configuration pins are shared with other function pins (LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0), some time must be given following the rising edge of reset in order to drive these device configuration input pins before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.

NOTE

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 4.4.

Table 4-1 C6654 Device Configuration Pins

CONFIGURATION PIN PIN NO. IPD/IPU(1) FUNCTIONAL DESCRIPTION
LENDIAN(1)(2) T25 IPU Device endian mode (LENDIAN).
  • 0 = Device operates in big endian mode
  • 1 = Device operates in little endian mode
BOOTMODE[12:0](1)(2) R25, R3, U25, T23, U24, T22, R21, U22, U23, V23, U21, T21, V22 IPD Method of boot.

Some pins may not be used by bootloader and can be used as general purpose config pins. Refer to the Bootloader for the C66x DSP User's Guide (SPRUGY5) for how to determine the device enumeration ID value.
PCIESSMODE[1:0](1)(2) W21, V21 IPD PCIe Subsystem mode selection.
  • 00 = PCIe in end point mode
  • 01 = PCIe legacy end point (support for legacy INTx)
  • 10 = PCIe in root complex mode
  • 11 = Reserved
PCIESSEN(1)(2) AD20 IPD PCIe subsystem enable/disable.
  • 0 = PCIE Subsystem is disabled
  • 1 = PCIE Subsystem is enabled
(1) Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 4.4.
(2) These signal names are the secondary functions of these pins.

4.2 Peripheral Selection After Device Reset

Several of the peripherals on the C6654 are controlled by the Power Sleep Controller (PSC). By default, the PCIe is held in reset and clock-gated. The memory in this module is also in a low-leakage sleep mode. Software is required to turn this memory on. The software enables the module (turns on clocks and de-asserts reset) before this module can be used.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User's Guide (SPRUGV4).

4.3 Device State Control Registers

The C6654 device has a set of registers that are used to provide the status or configure certain parts of its peripherals. These registers are shown in Table 4-2.

Table 4-2 Device State Control Registers

ADDRESS START ADDRESS END SIZE FIELD DESCRIPTION
0x02620000 0x02620007 8B Reserved
0x02620008 0x02620017 16B Reserved
0x02620018 0x0262001B 4B JTAGID See Section 4.3.3
0x0262001C 0x0262001F 4B Reserved
0x02620020 0x02620023 4B DEVSTAT See Section 4.3.1
0x02620024 0x02620037 20B Reserved
0x02620038 0x0262003B 4B KICK0 See Section 4.3.4
0x0262003C 0x0262003F 4B KICK1
0x02620040 0x02620043 4B DSP_BOOT_ADDR0 The boot address for C66x DSP CorePac0
0x02620044 0x02620047 4B Reserved Reserved
0x02620048 0x0262004B 4B Reserved
0x0262004C 0x0262004F 4B Reserved
0x02620050 0x02620053 4B Reserved
0x02620054 0x02620057 4B Reserved
0x02620058 0x0262005B 4B Reserved
0x0262005C 0x0262005F 4B Reserved
0x02620060 0x026200DF 128B Reserved
0x026200E0 0x0262010F 48B Reserved
0x02620110 0x02620117 8B MACID See Section 8.16
0x02620118 0x0262012F 24B Reserved
0x02620130 0x02620133 4B LRSTNMIPINSTAT_CLR See Section 4.3.6
0x02620134 0x02620137 4B RESET_STAT_CLR See Section 4.3.8
0x02620138 0x0262013B 4B Reserved
0x0262013C 0x0262013F 4B BOOTCOMPLETE See Section 4.3.9
0x02620140 0x02620143 4B Reserved
0x02620144 0x02620147 4B RESET_STAT See Section 4.3.7
0x02620148 0x0262014B 4B LRSTNMIPINSTAT See Section 4.3.5
0x0262014C 0x0262014F 4B DEVCFG See Section 4.3.2
0x02620150 0x02620153 4B PWRSTATECTL See Section 4.3.10
0x02620154 0x02620157 4B Reserved
0x02620158 0x0262015B 4B SMGII_SERDES_STS See Section 9.2
0x0262015C 0x0262015F 4B PCIE_SERDES_STS
0x02620160 0x02620163 4B Reserved
0x02620164 0x02620167 4B Reserved
0x02620168 0x0262016B 4B Reserved
0x0262016C 0x0262016F 4B UPP_CLOCK See Section 4.3.22
0x02620170 0x02620183 20B Reserved
0x02620184 0x0262018F 12B Reserved
0x02620190 0x02620193 4B Reserved
0x02620194 0x02620197 4B Reserved
0x02620198 0x0262019B 4B Reserved
0x0262019C 0x0262019F 4B Reserved
0x026201A0 0x026201A3 4B Reserved
0x026201A4 0x026201A7 4B Reserved
0x026201A8 0x026201AB 4B Reserved
0x026201AC 0x026201AF 4B Reserved
0x026201B0 0x026201B3 4B Reserved
0x026201B4 0x026201B7 4B Reserved
0x026201B8 0x026201BB 4B Reserved
0x026201BC 0x026201BF 4B Reserved
0x026201C0 0x026201C3 4B Reserved
0x026201C4 0x026201C7 4B Reserved
0x026201C8 0x026201CB 4B Reserved
0x026201CC 0x026201CF 4B Reserved
0x026201D0 0x026201FF 48B Reserved
0x02620200 0x02620203 4B NMIGR0 See Section 4.3.11
0x02620204 0x02620207 4B Reserved
0x02620208 0x0262020B 4B Reserved
0x0262020C 0x0262020F 4B Reserved
0x02620210 0x02620213 4B Reserved
0x02620214 0x02620217 4B Reserved
0x02620218 0x0262021B 4B Reserved
0x0262021C 0x0262021F 4B Reserved
0x02620220 0x0262023F 32B Reserved
0x02620240 0x02620243 4B IPCGR0 See Section 4.3.12
0x02620244 0x02620247 4B Reserved
0x02620248 0x0262024B 4B Reserved
0x0262024C 0x0262024F 4B Reserved
0x02620250 0x02620253 4B Reserved
0x02620254 0x02620257 4B Reserved
0x02620258 0x0262025B 4B Reserved
0x0262025C 0x0262025F 4B Reserved
0x02620260 0x0262027B 28B Reserved
0x0262027C 0x0262027F 4B IPCGRH See Section 4.3.14
0x02620280 0x02620283 4B IPCAR0 See Section 4.3.13
0x02620284 0x02620287 4B Reserved
0x02620288 0x0262028B 4B Reserved
0x0262028C 0x0262028F 4B Reserved
0x02620290 0x02620293 4B Reserved
0x02620294 0x02620297 4B Reserved
0x02620298 0x0262029B 4B Reserved
0x0262029C 0x0262029F 4B Reserved
0x026202A0 0x026202BB 28B Reserved
0x026202BC 0x026202BF 4B IPCARH See Section 4.3.15
0x026202C0 0x026202FF 64B Reserved
0x02620300 0x02620303 4B TINPSEL See Section 4.3.16

See Section 4.3.17

0x02620304 0x02620307 4B TOUTPSEL
0x02620308 0x0262030B 4B RSTMUX0 See Section 4.3.18
0x0262030C 0x0262030F 4B Reserved
0x02620310 0x02620313 4B Reserved
0x02620314 0x02620317 4B Reserved
0x02620318 0x0262031B 4B Reserved
0x0262031C 0x0262031F 4B Reserved
0x02620320 0x02620323 4B Reserved
0x02620324 0x02620327 4B Reserved
0x02620328 0x0262032B 4B MAINPLLCTL0 See Section 8.5
0x0262032C 0x0262032F 4B MAINPLLCTL1
0x02620330 0x02620333 4B DDR3PLLCTL0 See Section 8.6
0x02620334 0x02620337 4B DDR3PLLCTL1
0x02620338 0x0262033B 4B Reserved
0x0262033C 0x0262033F 4B Reserved
0x02620340 0x02620343 4B SGMII_SERDES_CFGPLL See Section 9.2
0x02620344 0x02620347 4B SGMII_SERDES_CFGRX0
0x02620348 0x0262034B 4B SGMII_SERDES_CFGTX0
0x0262034C 0x0262034F 4B Reserved
0x02620350 0x02620353 4B Reserved
0x02620354 0x02620357 4B Reserved
0x02620358 0x0262035B 4B PCIE_SERDES_CFGPLL
0x0262035C 0x0262035F 4B Reserved
0x02620360 0x02620363 4B Reserved
0x02620364 0x02620367 4B Reserved
0x02620368 0x0262036B 4B Reserved
0x0262036C 0x0262036F 4B Reserved
0x02620370 0x02620373 4B Reserved
0x02620374 0x02620377 4B Reserved
0x02620378 0x0262037B 4B Reserved
0x0262037C 0x0262037F 4B Reserved
0x02620380 0x02620383 4B Reserved
0x02620384 0x02620387 8B Reserved
0x026203B4 0x026203B7 4B Reserved
0x026203B8 0x026203BB 4B Reserved
0x026203BC 0x026203BF 4B Reserved
0x026203C0 0x026203C3 4B Reserved
0x026203C4 0x026203C7 4B Reserved
0x026203C8 0x026203CB 4B Reserved
0x026203CC 0x026203CF 4B Reserved
0x026203D0 0x026203D3 4B Reserved
0x026203D4 0x026203D7 4B Reserved
0x026203D8 0x026203DB 4B Reserved
0x026203DC 0x026203F7 28B Reserved
0x026203F8 0x026203FB 4B DEVSPEED See Section 4.3.19
0x026203FC 0x026203FF 4B Reserved
0x02620400 0x02620403 4B PKTDMA_PRI_ALLOC See Section 5.4
0x02620404 0x02620467 100B Reserved
0x02620468 0x0262057f 280B Reserved
0x02620580 0x02620583 4B PIN_CONTROL_0 See Section 4.3.20
0x02620584 0x02620587 4B PIN_CONTROL_1 See Section 4.3.21
0x02620588 0x0262058B 4B EMAC_UPP_PRI_ALLOC See Section 5.4

4.3.1 Device Status Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is shown in Figure 4-1 and described in Table 4-3.

Figure 4-1 Device Status Register
31 17 16 15 14 13 1 0
Reserved PCIESSEN PCIESSMODE
[1:0]		 BOOTMODE[12:0] LENDIAN
R-0 R-x R/W-xx R/W-xxxxxxxxxxxx R-x(1)
Legend: R = Read only; RW = Read/Write; -n = value after reset
(1) x indicates the bootstrap value latched via the external pin

Table 4-3 Device Status Register Field Descriptions

Bit Field Description
31-17 Reserved Reserved. Read only, writes have no effect.
16 PCIESSEN PCIe module enable
  • 0 = PCIe module disabled
  • 1 = PCIe module enabled
15-14 PCIESSMODE[1:0] PCIe Mode selection pins
  • 00b = PCIe in End-point mode
  • 01b = PCIe in Legacy End-point mode (support for legacy INTx)
  • 10b = PCIe in Root complex mode
  • 11b = Reserved
13-1 BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, refer to Section 3.5 and see the Bootloader for the C66x DSP User's Guide (SPRUGY5)
0 LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little Endian mode.
  • 0 = System is operating in Big Endian mode
  • 1 = System is operating in Little Endian mode

4.3.2 Device Configuration Register

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in Figure 4-2 and described in Table 4-4.

Figure 4-2 Device Configuration Register (DEVCFG)
31 1 0
Reserved SYSCLKOUTEN
R-0 R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-4 Device Configuration Register Field Descriptions

Bit Field Description
31-1 Reserved Reserved. Read only, writes have no effect.
0 SYSCLKOUTEN SYSCLKOUT Enable
  • 0 = No clock output
  • 1 = Clock output enabled (default)

4.3.3 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 4-3 and described in Table 4-5.

Figure 4-3 JTAG ID (JTAGID) Register
31 28 27 12 11 1 0
VARIANT PART NUMBER MANUFACTURER LSB
R-xxxxb R-1011 1001 0111 1010b 0000 0010 111b R-1
Legend: RW = Read/Write; R = Read only; -n = value after reset

Table 4-5 JTAG ID Register Field Descriptions

Bit Field Value Description
31-28 VARIANT xxxxb Variant (4-Bit) value.
27-12 PART NUMBER 1011 1001 0111 1010b Part Number for boundary scan
11-1 MANUFACTURER 0000 0010 111b Manufacturer
0 LSB 1b This bit is read as a 1 for C6654

NOTE

The value of the VARIANT and PART NUMBER fields depend on the silicon revision. See the Silicon Errata for details.

4.3.4 Kicker Mechanism (KICK0 and KICK1) Register

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg MMR values. When the kicker is locked (which it is initially after power on reset), none of the Bootcfg MMRs are writable (they are only readable). On the C6654, the exceptions to this are the IPC registers such as IPCGRx and IPCARx. These registers are not protected by the kicker mechanism. This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See Table 4-2 for the address location. Once released, then all the Bootcfg MMRs having write permissions are writable (the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg MMRs. To ensure protection of all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.

4.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on CORESEL. The LRESETNMI PIN Status Register is shown and described in the following tables.

Figure 4-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31 18 17 16 15 2 1 0
Reserved Reserved NMI0 Reserved Reserved LR0
R, +0000 0000 R-0 WC,+0 R, +0000 0000 WC,+0 WC,+0
Legend: R = Read only; -n = value after reset;

Table 4-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions

Bit Field Description
31-18 Reserved Reserved
17 Reserved Reserved
16 NMI0 CorePac0 in NMI
15-2 Reserved Reserved
1 Reserved Reserved
0 LR0 CorePac0 in Local Reset

4.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The LRESETNMI PIN Status Clear Register is shown and described in the following tables.

Figure 4-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31 18 17 16 15 2 1 0
Reserved Reserved NMI0 Reserved Reserved LR0
R, +0000 0000 WC,+0 WC,+0 R, +0000 0000 WC,+0 WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

Table 4-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions

Bit Field Description
31-18 Reserved Reserved
17 Reserved Reserved
16 NMI0 CorePac0 in NMI Clear
15-2 Reserved Reserved
1 Reserved Reserved
0 LR0 CorePac0 in Local Reset Clear

4.3.7 Reset Status (RESET_STAT) Register

The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

  • In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives a local reset without receiving a global reset.
  • In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

The Reset Status Register is shown and described in the following tables.

Figure 4-6 Reset Status Register (RESET_STAT)
31 30 2 1 0
GR Reserved Reserved LR0
R, +1 R, + 000 0000 0000 0000 0000 0000 R,+0 R,+0
Legend: R = Read only; -n = value after reset

Table 4-8 Reset Status Register (RESET_STAT) Field Descriptions

Bit Field Description
31 GR Global reset status
  • 0 = Device has not received a global reset.
  • 1 = Device received a global reset.
30-2 Reserved Reserved.
1 Reserved Reserved.
0 LR0 CorePac0 reset status
  • 0 = CorePac0 has not received a local reset.
  • 1 = CorePac0 received a local reset.

4.3.8 Reset Status Clear (RESET_STAT_CLR) Register

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown and described in the following tables.

Figure 4-7 Reset Status Clear Register (RESET_STAT_CLR)
31 30 2 1 0
GR Reserved Reserved LR0
RW, +0 R, + 000 0000 0000 0000 0000 0000 RW,+0 RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions

Bit Field Description
31 GR Global reset clear bit
  • 0 = Writing a 0 has no effect.
  • 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
30-2 Reserved Reserved.
1 Reserved Reserved.
0 LR0 CorePac0 reset clear bit
  • 0 = Writing a 0 has no effect.
  • 1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

4.3.9 Boot Complete (BOOTCOMPLETE) Register

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the completion of the ROM booting process. The Boot Complete Register is shown and described in the following tables.

Figure 4-8 Boot Complete Register (BOOTCOMPLETE)
31 2 1 0
Reserved Reserved BC0
R, + 0000 0000 0000 0000 0000 0000 RW,+0 RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions

Bit Field Description
31-2 Reserved Reserved.
1 Reserved Reserved
0 BC0 CorePac0 boot status
  • 0 = CorePac0 boot NOT complete
  • 1 = CorePac0 boot complete

The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before branching to the predefined location in memory.

4.3.10 Power State Control (PWRSTATECTL) Register

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices (SPRABI2) for more information. The Power State Control Register is shown in Figure 4-9 and described in Table 4-11.

Figure 4-9 Power State Control Register (PWRSTATECTL)
31 3 2 1 0
GENERAL_PURPOSE HIBERNATION
_MODE		 HIBERNATION STANDBY
RW, +0000 0000 0000 0000 0000 0000 0000 0 RW,+0 RW,+0 RW,+0
Legend: RW = Read/Write; -n = value after reset

Table 4-11 Power State Control Register (PWRSTATECTL) Field Descriptions

Bit Field Description
31-3 GENERAL_PURPOSE Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User's Guide (SPRUGY8).
2 HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.
  • 0 = Hibernation mode 1
  • 1 = Hibernation mode 2
1 HIBERNATION Indicates whether the device is in hibernation mode or not.
  • 0 = Not in hibernation mode
  • 1 = Hibernation mode
0 STANDBY Indicates whether the device is in standby mode or not.
  • 0 = Not in standby mode
  • 1 = Standby mode

4.3.11 NMI Event Generation to CorePac (NMIGRx) Register

NMIGRx registers are used for generating NMI events to the CorePac. The C6654 has only NMIGR0, which generates an NMI event to the CorePac. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and reads return 0 and have no other effect. The NMI Event Generation to CorePac Register is shown in Figure 4-10 and described in Table 4-12.

Figure 4-10 NMI Generation Register (NMIGRx)
31 1 0
Reserved NMIG
R, +0000 0000 0000 0000 0000 0000 0000 000 RW,+0
Legend: RW = Read/Write; -n = value after reset

Table 4-12 NMI Generation Register (NMIGRx) Field Descriptions

Bit Field Description
31-1 Reserved Reserved
0 NMIG NMI pulse generation.

Reads return 0

Writes:

  • 0 = No effect
  • 1 = Sends an NMI pulse to the CorePac

4.3.12 IPC Generation (IPCGRx) Registers

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6654 has only IPCGR0. This register can be used by external hosts to generate interrupts to the CorePac. A write of 1 to the IPCG field of the IPCGRx register will generate an interrupt pulse to the CorePac.

This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation Register is shown in Figure 4-11 and described in Table 4-13.

Figure 4-11 IPC Generation Registers (IPCGRx)
31 30 29 28 27 8 7 6 5 4 3 1 0
SRCS
27		 SRCS
26		 SRCS
25		 SRCS
24		 SRCS23 – SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG
RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-13 IPC Generation Registers (IPCGRx) Field Descriptions

Bit Field Description
31-4 SRCSx Interrupt source indication.

Reads return current value of internal register bit.

Writes:

  • 0 = No effect
  • 1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
0 IPCG Inter-DSP interrupt generation.

Reads return 0.

Writes:

  • 0 = No effect
  • 1 = Creates an Inter-DSP interrupt.

4.3.13 IPC Acknowledgement (IPCARx) Registers

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

The C6654 has only IPCAR0. This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in Figure 4-12 and described in Table 4-14.

Figure 4-12 IPC Acknowledgement Registers (IPCARx)
31 30 29 28 27 8 7 6 5 4 3 0
SRCC
27		 SRCC
26		 SRCC
25		 SRCC
24		 SRCC23 – SRCC4 SRCC3 SRCC2 SRCC1 SRCC0 Reserved
RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions

Bit Field Description
31-4 SRCCx Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

  • 0 = No effect
  • 1 = Clears both SRCCx and the corresponding SRCSx
3-0 Reserved Reserved

4.3.14 IPC Generation Host (IPCGRH) Register

The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.

The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle period. The IPC Generation Host Register is shown in Figure 4-13 and described in Table 4-15.

Figure 4-13 IPC Generation Registers (IPCGRH)
31 30 29 28 27 8 7 6 5 4 3 1 0
SRCS
27		 SRCS
26		 SRCS
25		 SRCS
24		 SRCS23 – SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG
RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-15 IPC Generation Registers (IPCGRH) Field Descriptions

Bit Field Description
31-4 SRCSx Interrupt source indication.

Reads return current value of internal register bit.

Writes:

  • 0 = No effect
  • 1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
0 IPCG Host interrupt generation.

Reads return 0.

Writes:

  • 0 = No effect
  • 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

4.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 4-14 and described in Table 4-16.

Figure 4-14 IPC Acknowledgement Register (IPCARH)
31 30 29 28 27 8 7 6 5 4 3 0
SRCC
27		 SRCC
26		 SRCC
25		 SRCC
24		 SRCC23 – SRCC4 SRCC3 SRCC2 SRCC1 SRCC0 Reserved
RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-16 IPC Acknowledgement Register (IPCARH) Field Descriptions

Bit Field Description
31-4 SRCCx Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

  • 0 = No effect
  • 1 = Clears both SRCCx and the corresponding SRCSx
3-0 Reserved Reserved

4.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown in Figure 4-15 and described in Table 4-17.

Figure 4-15 Timer Input Selection Register (TINPSEL)
31 16
Reserved
R, +1010 1010 1010 1010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TINPH
SEL7		 TINPL
SEL7		 TINPH
SEL6		 TINPL
SEL6		 TINPH
SEL5		 TINPL
SEL5		 TINPH
SEL4		 TINPL
SEL4		 TINPH
SEL3		 TINPL
SEL3		 TINPH
SEL2		 TINPL
SEL2		 TINPH
SEL1		 TINPL
SEL1		 TINPH
SEL0		 TINPL
SEL0
RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-17 Timer Input Selection Field Description (TINPSEL)

Bit Field Description
31-16 Reserved
  • Reserved
15 TINPHSEL7 Input select for TIMER7 high.
  • 0 = TIMI0
  • 1 = TIMI1
14 TINPLSEL7 Input select for TIMER7 low.
  • 0 = TIMI0
  • 1 = TIMI1
13 TINPHSEL6 Input select for TIMER6 high.
  • 0 = TIMI0
  • 1 = TIMI1
12 TINPLSEL6 Input select for TIMER6 low.
  • 0 = TIMI0
  • 1 = TIMI1
11 TINPHSEL5 Input select for TIMER5 high.
  • 0 = TIMI0
  • 1 = TIMI1
10 TINPLSEL5 Input select for TIMER5 low.
  • 0 = TIMI0
  • 1 = TIMI1
9 TINPHSEL4 Input select for TIMER4 high.
  • 0 = TIMI0
  • 1 = TIMI1
8 TINPLSEL4 Input select for TIMER4 low.
  • 0 = TIMI0
  • 1 = TIMI1
7 TINPHSEL3 Input select for TIMER3 high.
  • 0 = TIMI0
  • 1 = TIMI1
6 TINPLSEL3 Input select for TIMER3 low.
  • 0 = TIMI0
  • 1 = TIMI1
5 TINPHSEL2 Input select for TIMER2 high.
  • 0 = TIMI0
  • 1 = TIMI1
4 TINPLSEL2 Input select for TIMER2 low.
  • 0 = TIMI0
  • 1 = TIMI1
3 TINPHSEL1 Input select for TIMER1 high.
  • 0 = TIMI0
  • 1 = TIMI1
2 TINPLSEL1 Input select for TIMER1 low.
  • 0 = TIMI0
  • 1 = TIMI1
1 TINPHSEL0 Input select for TIMER0 high.
  • 0 = TIMI0
  • 1 = TIMI1
0 TINPLSEL0 Input select for TIMER0 low.
  • 0 = TIMI0
  • 1 = TIMI1

4.3.17 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in Figure 4-16 and described in Table 4-18.

Figure 4-16 Timer Output Selection Register (TOUTPSEL)
31 10 9 5 4 0
Reserved TOUTPSEL1 TOUTPSEL0
R,+000000000000000000000000 RW,+00001 RW,+00000
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-18 Timer Output Selection Field Description (TOUTPSEL)

Bit Field Description
31-10 Reserved Reserved
9-5 TOUTPSEL1 Output select for TIMO1
  • 0x0: TOUTL0
  • 0x1: TOUTH0
  • 0x2: TOUTL1
  • 0x3: TOUTH1
  • 0x4: TOUTL2
  • 0x5: TOUTH2
  • 0x6: TOUTL3
  • 0x7: TOUTH3
  • 0x8: TOUTL4
  • 0x9: TOUTH4
  • 0xA: TOUTL5
  • 0xB: TOUTH5
  • 0xC: TOUTL6
  • 0xD: TOUTH6
  • 0xE: TOUTL7
  • 0xF: TOUTH7
  • 0x10 to 0x1F: Reserved
4-0 TOUTPSEL0 Output select for TIMO0
  • 0x0: TOUTL0
  • 0x1: TOUTH0
  • 0x2: TOUTL1
  • 0x3: TOUTH1
  • 0x4: TOUTL2
  • 0x5: TOUTH2
  • 0x6: TOUTL3
  • 0x7: TOUTH3
  • 0x8: TOUTL4
  • 0x9: TOUTH4
  • 0xA: TOUTL5
  • 0xB: TOUTH5
  • 0xC: TOUTL6
  • 0xD: TOUTH6
  • 0xE: TOUTL7
  • 0xF: TOUTH7
  • 0x10 to 0x1F: Reserved

4.3.18 Reset Mux (RSTMUXx) Register

The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0. This register islocated in Bootcfg memory space. The Reset Mux Register is shown in Figure 4-17 and described in Table 4-19.

Figure 4-17 Reset Mux Register RSTMUXx
31 10 9 8 7 5 4 3 1 0
Reserved EVTSTATCLR Reserved DELAY EVTSTAT OMODE LOCK
R, +0000 0000 0000 0000 0000 00 RC, +0 R, +0 RW, +100 R, +0 RW, +000 RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear

Table 4-19 Reset Mux Register Field Descriptions

Bit Field Description
31-10 Reserved Reserved
9 EVTSTATCLR Clear event status
  • 0 = Writing 0 has no effect
  • 1 = Writing 1 clears the EVTSTAT bit
8 Reserved Reserved
7-5 DELAY Delay cycles between NMI & local reset
  • 000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b
  • 001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
  • 010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
  • 011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
  • 100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
  • 101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
  • 110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
  • 111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
4 EVTSTAT Event status.
  • 0 = No event received (Default)
  • 1 = WD timer event received by Reset Mux block
3-1 OMODE Timer event operation mode
  • 000b = WD timer event input to the reset mux block does not cause any output event (default)
  • 001b = Reserved
  • 010b = WD timer event input to the reset mux block causes local reset input to CorePac
  • 011b = WD timer event input to the reset mux block causes NMI input to CorePac
  • 100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay between NMI and local reset is set in DELAY bit field.
  • 101b = WD timer event input to the reset mux block causes device reset to C6654
  • 110b = Reserved
  • 111b = Reserved
0 LOCK Lock register fields
  • 0 = Register fields are not locked (default)
  • 1 = Register fields are locked until the next timer reset

4.3.19 Device Speed (DEVSPEED) Register

The Device Speed Register indicates the device speed grade. The Device Speed Register is shown in Figure 4-18 and described in Table 4-20.

Figure 4-18 Device Speed Register (DEVSPEED)
31 30 23 22 0
Reserved DEVSPEED Reserved
R-n R-n R-n
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-20 Device Speed Register Field Descriptions

Bit Field Description
31 Reserved Reserved. Read only
30-23 DEVSPEED Indicates the speed of the device (Read Only)
  • 1xxx xxxxb = 850 MHz
  • 01xx xxxxb = Reserved
  • 001x xxxxb = Reserved
  • 0001 xxxxb = Reserved
  • 0000 1xxxb = Reserved
  • 0000 01xxb = Reserved
  • 0000 001xb = Reserved
  • 0000 0001b = 850 MHz
  • 0000 0000b = 850 MHz
22-0 Reserved Reserved. Read only

4.3.20 Pin Control 0 (PIN_CONTROL_0) Register

The Pin Control 0 Register controls the pin muxing between GPIO[16:31] and TIMER / UART / SPI pins. The Pin Control 0 Register is shown in Figure 4-19 and described in Table 4-21.

Figure 4-19 Pin Control 0 Register (PIN_CONTROL_0)
31 30 29 28 27 26 25 24
GPIO31_SPIDOUT_MUX GPIO30_SPIDIN_MUX GPIO29_SPICS1_MUX GPIO28_SPICS0_MUX GPIO27_UARTRTS1_MUX GPIO26_UARTCTS1_MUX GPIO25_UARTTX1_MUX GPIO24_UARTRX1_MUX
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
23 22 21 20 19 18 17 16
GPIO23_UARTRTS0_MUX GPIO22_UARTCTS0_MUX GPIO21_UARTTX0_MUX GPIO20_UARTRX0_MUX GPIO19_TIMO1_MUX GPIO18_TIMO0_MUX GPIO17_TIMI1_MUX GPIO16_TIMI0_MUX
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
15 0
Reserved
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-21 Pin Control 0 Register Field Descriptions

Bit Field Description
31 GPIO31_SPIDOUT_MUX SPI or GPIO mux control
  • 0 = SPIDOUT pin enabled
  • 1 = GPIO31 pin enabled
30 GPIO30_SPIDIN_MUX SPI or GPIO mux control
  • 0 = SPIDIN pin enabled
  • 1 = GPIO30 pin enabled
29 GPIO29_SPICS1_MUX SPI or GPIO mux control
  • 0 = SPICS1 pin enabled
  • 1 = GPIO29 pin enabled
28 GPIO28_SPICS0_MUX SPI or GPIO mux control
  • 0 = SPICS0 pin enabled
  • 1 = GPIO28 pin enabled
27 GPIO27_UARTRTS1_MUX UART or GPIO mux control
  • 0 = UARTRTS1 pin enabled
  • 1 = GPIO27 pin enabled
26 GPIO26_UARTCTS1_MUX UART or GPIO mux control
  • 0 = UARTCTS1 pin enabled
  • 1 = GPIO26 pin enabled
25 GPIO25_UARTTX1_MUX UART or GPIO mux control
  • 0 = UARTTX1 pin enabled
  • 1 = GPIO25 pin enabled
24 GPIO24_UARTRX1_MUX UART or GPIO mux control
  • 0 = UARTRX1 pin enabled
  • 1 = GPIO24 pin enabled
23 GPIO23_UARTRTS0_MUX UART or GPIO mux control
  • 0 = UARTRTS0 pin enabled
  • 1 = GPIO23 pin enabled
22 GPIO22_UARTCTS0_MUX UART or GPIO mux control
  • 0 = UARTCTS0 pin enabled
  • 1 = GPIO22 pin enabled
21 GPIO21_UARTTX0_MUX UART or GPIO mux control
  • 0 = UARTTX0 pin enabled
  • 1 = GPIO21 pin enabled
20 GPIO20_UARTRX0_MUX UART or GPIO mux control
  • 0 = UARTRX0 pin enabled
  • 1 = GPIO20 pin enabled
19 GPIO19_TIMO1_MUX TIMER or GPIO mux control
  • 0 = TIMO1 pin enabled
  • 1 = GPIO19 pin enabled
18 GPIO18_TIMO0_MUX TIMER or GPIO mux control
  • 0 = TIMO0 pin enabled
  • 1 = GPIO18 pin enabled
17 GPIO17_TIMI1_MUX TIMER or GPIO mux control
  • 0 = TIMI1 pin enabled
  • 1 = GPIO17 pin enabled
16 GPIO16_TIMI0_MUX TIMER or GPIO mux control
  • 0 = TIMI0 pin enabled
  • 1 = GPIO16 pin enabled
15-0 Reserved Reserved

4.3.21 Pin Control 1 (PIN_CONTROL_1) Register

The Pin Control 1 Register controls the pin muxing between uPP and EMIF16 pins. The Pin Control 1 Register is shown in Figure 4-20 and described in Table 4-22.

Figure 4-20 Pin Control 1Register (PIN_CONTROL_1)
31 1 0
Reserved UPP_EMIF16_MUX
R-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-22 Pin Control 1 Register Field Descriptions

Bit Field Description
31-1 Reserved Reserved
0 UPP_EMIF_MUX uPP or EMIF16 mux control
  • 0 = EMIF16 pins enabled
  • 1 = uPP pins enabled

4.3.22 uPP Clock Source (UPP_CLOCK) Register

The uPP Clock Source Register controls whether the uPP transmit clock is internally or externally sourced. The uPP Clock Source Register is shown in Figure 4-21 and described in Table 4-23.

Figure 4-21 uPP Clock Source Register (UPP_CLOCK)
31 1 0
Reserved UPP_TX_CLKSRC
R-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 4-23 uPP Clock Source Register Field Descriptions

Bit Field Description
31-1 Reserved Reserved
0 UPP_TX_CLKSRC uPP clock source selection
  • 0 = from internal SYSCLK4 (CPU/3)
  • 1 = from external UPP_2XTXCLK pin

4.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

  • Device Configuration Pins: If the pin is both routed out and is not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
  • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 4-1), if they are both routed out and are not driven (in Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the DVDD rail.

For most systems:

  • A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
  • A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for the C6654 device, see Section 7.3.

To determine which pins on the device include internal pullup/pulldown resistors, see Table 3-39.