ZHCSH87B September   2017  – February 2020 TMP461-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
    1.     简化框图
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Two-Wire Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Measurement Data
        1. 7.3.1.1 Standard Binary to Decimal Temperature Data Calculation Example
        2. 7.3.1.2 Standard Decimal to Binary Temperature Data Calculation Example
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 Differential Input Capacitance
      4. 7.3.4 Filtering
      5. 7.3.5 Sensor Fault
      6. 7.3.6 ALERT and THERM Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Bus Overview
        2. 7.5.1.2 Bus Definitions
        3. 7.5.1.3 Serial Bus Address
        4. 7.5.1.4 Read and Write Operations
        5. 7.5.1.5 Timeout Function
        6. 7.5.1.6 High-Speed Mode
      2. 7.5.2 General-Call Reset
    6. 7.6 Register Map
      1. 7.6.1 Register Information
        1. 7.6.1.1  Pointer Register
        2. 7.6.1.2  Local and Remote Temperature Registers
        3. 7.6.1.3  Status Register
        4. 7.6.1.4  Configuration Register
        5. 7.6.1.5  Conversion Rate Register
        6. 7.6.1.6  One-Shot Start Register
        7. 7.6.1.7  Channel Enable Register
        8. 7.6.1.8  Consecutive ALERT Register
        9. 7.6.1.9  η-Factor Correction Register
        10. 7.6.1.10 Remote Temperature Offset Register
        11. 7.6.1.11 Manufacturer Identification Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Radiation Environments
      1. 8.3.1 Single Event Latch-Up
      2. 8.3.2 Single Event Functional Interrupt
      3. 8.3.3 Single Event Upset
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1.2 Bus Definitions

The TMP461-SP device is two-wire- and SMBus-compatible. Figure 15 and Figure 16 illustrate the timing for various operations on the TMP461-SP device. The bus definitions are as follows:

    Bus Idle: Both SDA and SCL lines remain high.
    Start Data Transfer:A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition.
    Stop Data Transfer: A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition.
    Data Transfer:The number of data bytes transferred between a start and stop condition is not limited and is determined by the master device. The receiver acknowledges the data transfer.
    Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a master receive, data transfer termination can be signaled by the master generating a not-acknowledge on the last byte that is transmitted by the slave.
TMP461-SP ai_tim_2wire_write_bos686.gif
1. Slave address 1001100 is shown.
Figure 15. Two-Wire Timing Diagram for Write Word Format
TMP461-SP ai_tim_2wire_1byte_bosa686.gif
1. Slave address 1001100 is shown.
2. The master must leave SDA high to terminate a single-byte read operation.
Figure 16. Two-Wire Timing Diagram for Single-Byte Read Format