ZHCSDM0B October   2013  – December 2014 TLV62565 , TLV62566

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1 Power Save Mode
      2. 10.3.2 Enabling/Disabling the Device
      3. 10.3.3 Soft Start
      4. 10.3.4 Switch Current Limit
      5. 10.3.5 Power Good
    4. 10.4 Device Functional Modes
      1. 10.4.1 Under Voltage Lockout
      2. 10.4.2 Thermal Shutdown
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Output Filter Design
        2. 11.2.1.2 Inductor Selection
        3. 11.2.1.3 Input and Output Capacitor Selection
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Setting the Output Voltage
        2. 11.2.2.2 Loop Stability
      3. 11.2.3 Application Performance Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14器件和文档支持
    1. 14.1 器件支持
      1. 14.1.1 第三方产品免责声明
    2. 14.2 文档支持
      1. 14.2.1 相关文档
    3. 14.3 相关链接
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 术语表
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Specifications

8.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage(2) VIN, EN,PG –0.3 7 V
SW –0.3 VIN+0.3 V
FB –0.3 3.6 V
Sink current, IPG PG 660 µA
Continuous total power dissipation See Thermal Information
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions(1)

MIN TYP MAX UNIT
VIN Input voltage, VIN 2.7 5.5 V
TA Operating ambient temperature –40 85 °C
(1) Refer to the Application and Implementation section for further information.

8.4 Thermal Information

THERMAL METRIC(1) TLV62565, TLV62566 UNIT
DBV (5 Pins)
RθJA Junction-to-ambient thermal resistance 208.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.7
RθJB Junction-to-board thermal resistance 36.1
ψJT Junction-to-top characterization parameter 2.3
ψJB Junction-to-board characterization parameter 35.3
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Over recommended free-air temperature range, VIN = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage 2.7 5.5 V
IQ Quiescent current into VIN pin IOUT = 0 mA, Not switching 50 uA
VUVLO Under voltage lock out VIN falling 2.2 2.3 V
Under voltage lock out hysteresis 200 mV
TJSD Thermal shutdown Junction temperature rising 150 °C
Thermal shutdown hysteresis Junction temperature falling below TJSD 20
LOGIC INTERFACE, TLV62565
VIH High-level input voltage 2.7 V ≤ VIN ≤ 5.5 V 1.2 V
VIL Low-level input voltage 2.7 V ≤ VIN ≤ 5.5 V 0.4 V
ISD Shutdown current into VIN pin EN = LOW 0.1 1 µA
IEN,LKG EN leakage current 0.01 0.16 µA
POWER GOOD, TLV62566
VPG Power Good low threshold VFB falling referenced to VFB nominal 90%
Power Good high threshold VFB risng referenced to VFB nominal 95%
VL Low level voltage Isink = 500 µA 0.4 V
IPG,LKG PG Leakage current VPG = 5.0 V 0.01 0.17 µA
OUTPUT
VOUT Output voltage 0.6 DMAX.VIN V
VFB Feedback regulation voltage PWM operation, TA = -40°C to 85°C 0.588 0.6 0.612 V
PWM operation, TA = 85°C 0.594 0.6 0.606 V
PFM comparator threshold 0.9%
IFB Feedback input bias current VFB = 0.6 V 10 100 nA
RDS(on) High-side FET on resistance ISW = 500 mA, VIN = 3.6 V 173 mΩ
Low-side FET on resistance ISW = 500 mA, VIN = 3.6 V 105
ILIM,LS Low-side FET valley current limit 1.5 A
ILIM,HS High-side FET peak current limit 1.8 A
fSW Switching frequency 1.5 MHz
DMAX Maximum duty cycle 95%
tOFF,MIN Minimum off time 40 ns

8.6 Typical Characteristics

Table 1. Table of Graphs

FIGURE
Efficiency vs Load current (VOUT = 1.8 V, VIN = 2.7 V, 3.6 V, 5.5 V) Figure 1
vs Load current (VOUT = 1.2 V, VIN = 2.7 V, 3.6 V, 5.5 V) Figure 2
vs Load current (VOUT = 3.3 V, VIN = 4.2 V, 5.5 V) Figure 3
Output voltage vs Input voltage (Line regulation, VOUT = 1.8 V, Load = 0.5 A,1 A,1.5 A) Figure 4
vs Load current (Load regulation, VOUT = 1.8 V, VIN = 2.7 V, 3.6 V, 5.5 V) Figure 5
Quiescent current vs Input voltage Figure 6
RDS(on) vs Input voltage, High-Side FET Figure 7
vs Input voltage, Low-Side FET Figure 8
Switching frequency vs Load current, VOUT = 1.8 V Figure 9
TLV62565 TLV62566 C001_eff_SLVSBC1.png
Figure 1. Efficiency vs Load Current
TLV62565 TLV62566 C003_eff_SLVSBC1.png
Figure 3. Efficiency vs Load Current
TLV62565 TLV62566 C004_Vout_SLVSBC1.png
Figure 5. Output Voltage vs Load Current
TLV62565 TLV62566 C007_Rdson_SLVSBC1.png
Figure 7. High-Side FET RDS(on) vs Input Voltage
TLV62565 TLV62566 C0010_Freq_SLVSBC1.png
Figure 9. Switching Frequency vs Load Current
TLV62565 TLV62566 C002_eff_SLVSBC1.png
Figure 2. Efficiency vs Load Current
TLV62565 TLV62566 C011_Vout_SLVSBC1.png
Figure 4. Output Voltage vs Input Voltage
TLV62565 TLV62566 C009_IQ_SLVSBC1.png
Figure 6. Quiescent Current vs Input Voltage
TLV62565 TLV62566 C008_Rdson_SLVSBC1.png
Figure 8. Low-Side FET RDS(on) vs Input Voltage