ZHCSDM0B October   2013  – December 2014 TLV62565 , TLV62566


  1. 特性
  2. 应用
  3. 说明
  4. 简化电路原理图
  5. 修订历史记录
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1 Power Save Mode
      2. 10.3.2 Enabling/Disabling the Device
      3. 10.3.3 Soft Start
      4. 10.3.4 Switch Current Limit
      5. 10.3.5 Power Good
    4. 10.4 Device Functional Modes
      1. 10.4.1 Under Voltage Lockout
      2. 10.4.2 Thermal Shutdown
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. Output Filter Design
        2. Inductor Selection
        3. Input and Output Capacitor Selection
      2. 11.2.2 Detailed Design Procedure
        1. Setting the Output Voltage
        2. Loop Stability
      3. 11.2.3 Application Performance Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14器件和文档支持
    1. 14.1 器件支持
      1. 14.1.1 第三方产品免责声明
    2. 14.2 文档支持
      1. 14.2.1 相关文档
    3. 14.3 相关链接
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 术语表
  15. 15机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

11 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

11.1 Application Information

The TLV6256x devices are synchronous step-down converters optimized for small solution size and high efficiency. The devices integrate switches capable of delivering an output current up to 1.5 A.

11.2 Typical Application

TLV62565 2.7-V to 5.5-V input, 1.2-V output converter.

TLV62565 TLV62566 typ_app_TLV62565_1p2V.gifFigure 15. TLV62565 1.2-V Output Application

11.2.1 Design Requirements Output Filter Design

The inductor and output capacitor together provide a low-pass frequency filter. To simplify this process, Table 3 outlines possible inductor and capacitor value combinations.

Table 3. Matrix of Output Capacitor and Inductor Combinations

L [µH](1) COUT [µF](2)(3)
4.7 10 22 47 100
2.2 +(4) +(4) +(4)
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
(3) For low output voltage applications (≤ 1.2 V), more output capacitance is recommended (usually ≥ 22 µF) for smaller ripple.
(4) Typical application configuration. '+' indicates recommended filter combinations. Inductor Selection

The main parameters for inductor selection is inductor value and then saturation current of the inductor. To calculate the maximum inductor current under static load conditions, Equation 2 is given:

Equation 2. TLV62565 TLV62566 Eq_IL_peak_PWM_lvsae8.gif


  • IOUT,MAX is the maximum output current
  • ΔIL is the inductor current ripple
  • fSW is the switching frequency
  • L is the inductor value

It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate inductor. The recommended inductors are listed in Table 4.

Table 4. List of Recommended Inductors

L x W x H [mm3]
[mΩ typ]
2.2 2500 4 x 3.7 x 1.65 49 LQH44PN2R2MP0 Murata
2.2 3000 4 x 4 x 1.8 50 NRS4018T2R2MDGJ Taiyo Yuden Input and Output Capacitor Selection

The input capacitor is the low impedance energy source for the converter that helps provide stable operation. The closer the input capacitor is placed to the VIN and GND pins, the lower the switch ring. A low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-µF input capacitance is sufficient; a larger value reduces input voltage ripple.

The architecture of the TLV62565/6 allow use of tiny ceramic-type output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. The TLV62565/6 are designed to operate with an output capacitance of 10 µF to 47 µF, as outlined in Table 3.

11.2.2 Detailed Design Procedure Setting the Output Voltage

An external resistor divider is used to set output voltage. By selecting R1 and R2, the output voltage is programmed to the desired value. When the output voltage is regulated, the typical voltage at the FB pin is VFB. Equation 3, Equation 4, and Equation 5 can be used to calculate R1 and R2.

When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of 5 μA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase current consumption.

Equation 3. TLV62565 TLV62566 Eq_Vo.gif
Equation 4. TLV62565 TLV62566 Eq_Vo_2.gif
Equation 5. TLV62565 TLV62566 Eq_Vo_3.gif Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

  • Switching node, SW
  • Inductor current, IL
  • Output ripple voltage, VOUT(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. Applications with the recommended L-C combinations in Table 3 are designed for good loop stability as well as fast load transient response.

As a next step in the evaluation of the regulation loop, the load transient response is illustrated. The TLV62565/6 use a constant on time with valley current mode control, so the on time of the high-side MOSFET is relatively consistent from cycle to cycle when a load transient occurs. Whereas the off time adjusts dynamically in accordance with the instantaneous load change and brings VOUT back to the regulated value.

During recovery time, VOUT can be monitored for settling time, overshoot, or ringing which helps judge the stability of the converter. Without any ringing, the loop usually has more than 45° of phase margin.

11.2.3 Application Performance Curves

TLV62565 TLV62566 G001_PWM_SLVSBC1.gif
Figure 16. Typical Application (PWM Mode)
TLV62565 TLV62566 G003_PFM_SLVSBC1.gif
Figure 18. Typical Application (PFM Mode)
TLV62565 TLV62566 G008_Loadtran2_SLVSBC1.gif
Figure 20. Load Transient
TLV62565 TLV62566 G005_PGStartup_SLVSBC1.gif
Figure 22. Start Up (Power Good)
TLV62565 TLV62566 G002_PFM_SLVSBC1.gif
Figure 17. Typical Application (PFM Mode)
TLV62565 TLV62566 G007_Loadtran1_SLVSBC1.gif
Figure 19. Load Transient
TLV62565 TLV62566 G004_ENStartup_SLVSBC1.gif
Figure 21. Start Up
TLV62565 TLV62566 G006_Short_SLVSBC1.gif
Figure 23. Short Circuit Protection