The TLV62565/6 device family includes two high-efficiency synchronous step-down converters. Each device operates with an adaptive on-time control scheme, which is able to dynamically adjust the on-time duration based on the input voltage and output voltage so that it can achieve relative constant frequency operation. The device operates at typically 1.5-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required on time for the high-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. At the beginning of each switching cycle, the high-side switch is turned on and the inductor current ramps up to a peak current that is defined by on time and inductance. In the second phase, once the on time expires, the high-side switch is turned off while the low-side switch is being turned on. The current through the inductor then decays until triggering the valley current limit determined by the output of the error amplifier. Once this occurs, the on timer is set to turn the high-side switch back on again and the cycle is repeated.
The TLV62565/6 device family offers excellent load transient response with a unique fast response constant on-time valley current mode. The switching frequency changes during load transition so that the output voltage comes back in regulation faster than a traditional fixed PWM control scheme. Figure 10 shows the operation principles of the load transient response of the TLV62565/6. Internal loop compensation is integrated which simplifies the design process while minimizing the number of external components. At light load currents the device automatically operates in Power Save Mode with pulse frequency modulation (PFM).
The device integrates a Power Save Mode with PFM to improve efficiency at light load. In Power Save Mode, the device only switches when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and stops switching when the output voltage is higher than the set threshold voltage. PFM is exited and PWM mode entered in case the output current can no longer be supported in Power Save Mode. The threshold of the PFM comparator is typically 0.9% higher than the normal reference voltage. Figure 13 shows the details of PFM/PWM mode transition.
The device is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. The EN input must be terminated and should not be left floating.
After enabling the device, internal soft-start circuitry monotonically ramps up the output voltage which reaches nominal output voltage during a soft-start time of 250 µs (typical). This avoids excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.
If the output voltage is not reached within the soft-start time, such as in the case of a heavy load, the converter enters regular operation. The TLV62565/6 are able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.
The switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.
The TLV62565/6 adopt valley current control by sensing the current of the low-side MOSFET. Once the low-side valley switch current limit is tripped, the low-side MOSFET is turned off and limits the inductor's valley current. The high-side current is also limited which is determined by the on time of the high-side MOSFET and inductor value calculated by Equation 1. For example, with 3.6 VIN to 1.8 VOUT and 2.2-µH specification, the peak current limit is approximately 1.97 A with a typical valley current limit of 1.7 A.
Additionally, there is a secondary high-side current limit (typical 2 A) to prevent the current from going too high, which is shown in Figure 14. Due to the internal propagation delay, the real current limit value might be higher than the static current limit in the electrical characteristics table.
The TLV62566 integrates a Power Good output going low when the output voltage is below its nominal value. The Power Good output stays high impedance once the output is above 95% of the regulated voltage and is low once the output voltage falls below typically 90% of the regulated voltage. The PG pin is an open drain output and is specified to sink typically up to 0.5 mA. The Power Good output requires a pull-up resistor connected to any voltage lower than 5.5 V. When the device is off due to UVLO or thermal shutdown, the PG pin is pulled to logic low.
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.
The device enters thermal shutdown once the junction temperature exceeds typically TJSD. Once the device temperature falls below the threshold with hysteresis, the device returns to normal operation automatically. Power Good is pulled low when thermal protection is triggered.