ZHCSGU7 October   2017 TLV3544-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV3544-Q1
    5. 6.5 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TLV3544-Q1 Comparison
      2. 7.3.2 Operating Voltage
      3. 7.3.3 Rail-to-Rail Input
      4. 7.3.4 Rail-to-Rail Output
      5. 7.3.5 Output Drive
      6. 7.3.6 Video
      7. 7.3.7 Driving Analog-to-Digital converters
      8. 7.3.8 Capacitive Load and Stability
      9. 7.3.9 Wideband Transimpedance Amplifier
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optimizing the Transimpedance Circuit
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11器件和文档支持
    1. 11.1 文档支持
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply voltage, V+ to V− 7.5 V
Signal input terminals(2) (V−) − (0.5) (V+) + 0.5
Current Signal input terminals(2) –10 10 mA
Output short circuit(3) Continuous
Temperature Operating, TA –55 150 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1000 V
Charged-device model (CDM), per AEC Q100-011 ±250
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage, V– to V+ 2.5 5.5 V
Specified temperature –40 125 °C

6.4 Thermal Information: TLV3544-Q1

THERMAL METRIC TLV3544-Q1 UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 92.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.5 °C/W
RθJB Junction-to-board thermal resistance 33.6 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 33.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

6.5 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply

At TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V, at TA = 25°C ±2 ±10 mV
dVOS/dT Input offset voltage vs temperature VS = 5 V, at TA = −40°C to +125°C ±4.5 µV/°C
PSRR Input offset voltage vs power supply VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V		 ±200 ±800 µV/V
VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V,
at TA = −40°C to +125°C		 ±900
INPUT BIAS CURRENT
IB Input bias current 3 pA
IOS Input offset current ±1 pA
NOISE
en Input voltage noise density f = 1 MHz 7.5 nV/√Hz
in Current noise density f = 1 MHz 50 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage (V−) − 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = 25°C		 66 80 dB
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = 25°C		 56 68
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-mode 1013 || 2 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop gain VS = 5.5 V, 0.3 V < VO < 4.7 V,
at TA = 25°C		 94 110 dB
VS = 5 V, 0.4 V < VO < 4.6 V,
at TA = –40°C to +125°C		 90
FREQUENCY RESPONSE
f−3dB Small-signal bandwidth At G = +1, VO = 100 mVPP,
RF = 25 Ω		 250 MHz
At G = +2, VO = 100 mVPP 90
GBW Gain-bandwidth product G = +10 100 MHz
f0.1dB Bandwidth for 0.1-dB gain flatness At G = +2, VO = 100 mVPP 40 MHz
SR Slew rate VS = 5 V, G = +1, 4-V step 150 V/µs
VS = 5 V, G = +1, 2-V step 130
VS = 3 V, G = +1, 2-V step 110
Rise-and-fall time At G = +1, VO = 200 mVPP,
10% to 90%		 2 ns
At G = +1, VO = 2 VPP, 10% to 90% 11
Settling time 0.1%, VS = 5 V, G = +1,
2-V output step		 30 ns
0.01%, VS = 5 V, G = +1,
2-V output step		 60
Overload recovery time VIN × Gain = VS 5 ns
FREQUENCY RESPONSE, continued
Harmonic distortion Second harmonic At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V		 –75 dBc
Third harmonic At G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V		 –83
Differential gain error NTSC, RL = 150 Ω 0.02%
Differential phase error NTSC, RL = 150 Ω 0.09 °
Channel-to-channel crosstalk TLV3544-Q1 f = 5 MHz –84 dB
OUTPUT
Voltage output swing from rail VS = 5 V, RL = 1 kΩ, AOL > 94 dB,
at TA = 25°C		 0.1 0.3 V
IO Output current(1)(2) VS = 5 V 100 mA
VS = 3 V 50 mA
Closed-loop output impedance f < 100 kHz 0.05 Ω
RO Open-loop output resistance 35 Ω
POWER SUPPLY
VS Specified voltage 2.7 5 V
Operating voltage 2.5 5.5
IQ Quiescent current (per amplifier) At TA = 25°C, VS = 5 V, enabled,
IO = 0		 5.2 6.5 mA
THERMAL SHUTDOWN – JUNCTION TEMPERATURE
Shutdown 160 °C
Reset from shutdown 140 °C
THERMAL RANGE
Specified –40 125 °C
Operating –55 150 °C
Storage –65 150 °C
(1) See typical characteristic curves, Output Voltage Swing vs Output Current (Figure 20 and Figure 22).
(2) Specified by design.

6.6 Typical Characteristics

At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
TLV3544-Q1 tc_noninverting_sm-signal_fqcy_resp_bos233.gif
Figure 1. Noninverting Small-Signal Frequency Response
TLV3544-Q1 tc_noninverting_sm-signal_step_resp_bos233.gif
Figure 3. Noninverting Small-Signal Step Response
TLV3544-Q1 tc_gain_flatness_bos233.gif
Figure 5. 0.1-dB Gain Flatness
TLV3544-Q1 tc_harmonic_distortion_noninverting_gain_bos233.gif
Figure 7. Harmonic Distortion vs Noninverting Gain
TLV3544-Q1 tc_harmonic_distortion_frequency_bos233.gif
Figure 9. Harmonic Distortion vs Frequency
TLV3544-Q1 tc_voltage_current_noise_spec_density_fqcy_bos233.gif
Figure 11. Input Voltage and Current Noise
Spectral Density vs Frequency
TLV3544-Q1 tc_frequency_resp_cloads_bos233.gif
Figure 13. Frequency Response for Various CL
TLV3544-Q1 tc_frequency_resp_cload_bos897.gif
Figure 15. Frequency Response vs Capacitive Load
TLV3544-Q1 tc_open_loop_gain_phase_bos233.gif
Figure 17. Open-Loop Gain and Phase
TLV3544-Q1 tc_ibias_temp_bos233.gif
Figure 19. Input Bias Current vs Temperature
TLV3544-Q1 tc_isupply_temp_bos233.gif
Figure 21. Supply Current vs Temperature
TLV3544-Q1 tc_closed_loop_output_imped_fqcy_bos897.gif
Figure 23. Closed-Loop Output Impedance vs Frequency
TLV3544-Q1 tc_output_settling_time_bos233.gif
Figure 25. Output Settling Time to 0.1%
TLV3544-Q1 tc_voffset_prod_distribution_bos233.gif
Figure 27. Offset Voltage Production Distribution
TLV3544-Q1 tc_crosstalk_bos897.gif
Figure 29. Channel-to-Channel Crosstalk
TLV3544-Q1 tc_inverting_sm-signal_fqcy_resp_bos233.gif
Figure 2. Inverting Small-Signal Frequency Response
TLV3544-Q1 tc_noninverting_lg-signal_step_resp_bos233.gif
Figure 4. Noninverting Large-Signal Step Response
TLV3544-Q1 tc_harmonic_distortion_vout_bos233.gif
Figure 6. Harmonic Distortion vs Output Voltage
TLV3544-Q1 tc_harmonic_distortion_inverting_gain_bos233.gif
Figure 8. Harmonic Distortion vs Inverting Gain
TLV3544-Q1 tc_harmonic_distortion_rload_bos233.gif
Figure 10. Harmonic Distortion vs Load Resistance
TLV3544-Q1 tc_frequency_resp_rloads_bos233.gif
Figure 12. Frequency Response for Various RL
TLV3544-Q1 tc_recommended_rs_cload_bos897.gif
Figure 14. Recommended RS vs Capacitive Load
TLV3544-Q1 tc_cmrr_psrr_fqcy_bos233.gif
Figure 16. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Frequency
TLV3544-Q1 tc_differential_gain_phase_bos233.gif
Figure 18. Composite Video Differential Gain and Phase
TLV3544-Q1 tc_3V_vout_swing_iout_bos233.gif
Figure 20. Output Voltage Swing vs Output Current for
VS = 3 V
TLV3544-Q1 tc_5V_vout_swing_iout_bos233.gif
Figure 22. Output Voltage Swing vs Output Current for
VS = 5 V
TLV3544-Q1 tc_vout_max_fqcy_bos233.gif
Figure 24. Maximum Output Voltage vs Frequency
TLV3544-Q1 tc_open_loop_gain_temp_bos233.gif
Figure 26. Open-Loop Gain vs Temperature
TLV3544-Q1 tc_cmrr_psrr_temp_bos233.gif
Figure 28. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Temperature