SLOS823D December   2012  – March 2020 THS4531A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     1-kHz FFT Plot on Audio Analyzer
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 2.7 V
    6. 7.6 Electrical Characteristics: VS = 5 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 Typical Characteristics: VS = 2.7 V
      2. 7.7.2 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
        1. 8.3.1.1 Setting the Output Common-Mode Voltage
      2. 8.3.2 Power Down
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Frequency Response, and Output Impedance
      2. 9.1.2  Distortion
      3. 9.1.3  Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turnon and Turnoff Time
      4. 9.1.4  Common-Mode and Power Supply Rejection
      5. 9.1.5  VOCM Input
      6. 9.1.6  Balance Error
      7. 9.1.7  Single-Supply Operation
      8. 9.1.8  Low-Power Applications and the Effects of Resistor Values on Bandwidth
      9. 9.1.9  Driving Capacitive Loads
      10. 9.1.10 Audio Performance
      11. 9.1.11 Audio On and Off Pop Performance
    2. 9.2 Typical Applications
      1. 9.2.1 SAR ADC Performance: THS4531A and ADS8321 Combined Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Audio ADC Driver Performance: THS4531A and PCM4204 Combined Performance
        1. 9.2.2.1 Detailed Design Procedure
        2. 9.2.2.2 Application Curves
      3. 9.2.3 SAR ADC Performance: THS4531A and ADS7945 Combined Performance
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
      4. 9.2.4 Differential-Input to Differential-Output Amplifier
        1. 9.2.4.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
      5. 9.2.5 Single-Ended to Differential FDA Configuration
        1. 9.2.5.1 Input Impedance
      6. 9.2.6 Single-Ended Input to Differential Output Amplifier
        1. 9.2.6.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.2.6.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.2.6.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
      7. 9.2.7 Differential Input to Single-Ended Output Amplifier
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics: VS = 2.7 V

Test conditions at TA ≈ 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V, single-ended input, differential output, and output referenced to mid-supply, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST
LEVEL(2)
AC PERFORMANCE
Small-signal bandwidth VOUT = 100 mVPP, G = 1 34 MHz C
VOUT = 100 mVPP, G = 2 16
VOUT = 100 mVPP, G = 5 6
VOUT = 100 mVPP, G = 10 2.7
Gain-bandwidth product VOUT = 100 mVPP, G = 10 27 MHz C
Large-signal bandwidth VOUT = 2 VPP, G = 1 34 MHz C
Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 1 12 MHz C
Slew rate, rise/fall, 25% to 75% VOUT = 2-V step 190/320 V/µs C
Rise/fall time, 10% to 90% VOUT = 2-V step 6 ns C
Settling time to 1% VOUT = 2-V step 25 ns C
Settling time to 0.1% VOUT = 2-V step 60 ns C
Settling time to 0.01% VOUT = 2-V step 150 ns C
Overshoot/undershoot VOUT = 2-V step 1% C
2nd-order harmonic distortion f = 1 kHz, VOUT = 2 VPP –122 dBc C
f = 10 kHz –127
f = 1 MHz –59
3rd-order harmonic distortion f = 1 kHz, VOUT = 2 VPP –136 dBc C
f = 10 kHz –135
f = 1 MHz –70
2nd-order intermodulation distortion f = 1 MHz, 200-kHz tone spacing,
VOUT = 1 Vpp each tone		 –83 dBc C
3rd-order intermodulation distortion f = 1 MHz, 200-kHz tone spacing,
VOUT = 1 Vpp each tone		 –81 dBc C
Input voltage noise f = 1 kHz 10 nV/√Hz C
Voltage noise 1/f corner frequency 45 Hz C
Input current noise f = 100 kHz 0.25 pA/√Hz C
Current noise 1/f corner frequency 6.5 kHz C
Overdrive recovery time Overdrive = 0.5 V 65 ns C
Output balance error VOUT = 100 mV, f = 1 MHz –65 dB C
Closed-loop output impedance f = 1 MHz (differential) 2.5 Ω C
DC PERFORMANCE
Open-loop voltage gain (AOL) 100 113 dB A
Input-referred offset voltage TA = 25°C –400 ±100 400 µV A
TA = 0°C to +70°C –715 715 B
TA = –40°C to +85°C –855 855
TA = –40°C to +125°C –1300 1300
Input offset voltage drift(3) TA = 0°C to 70°C –7 ±2 7 µV/°C B
TA = –40°C to +85°C –7 ±2 7
TA = –40°C to +125°C –9 ±3 9
Input bias current(1) TA = 25°C 200 250 nA A
TA = 0°C to +70°C 275 B
TA = –40°C to +85°C 286
TA = –40°C to +125°C 305
Input bias current drift(3) TA = 0°C to +70°C 0.45 0.55 nA/°C B
TA = –40°C to +85°C 0.45 0.55
TA = –40°C to +125°C 0.45 0.55
Input offset current TA = 25°C –50 ±5 50 nA A
TA = 0°C to +70°C –55 55 B
TA = –40°C to +85°C –57 57
TA = –40°C to +125°C –60 60
Input offset current drift(3) TA = 0°C to +70°C –0.1 ±0.03 0.1 nA/°C B
TA = –40°C to +85°C –0.1 ±0.03 0.1
TA = –40°C to +125°C –0.1 ±0.03 0.1
INPUT
Common-mode input low TA = 25°C, CMRR > 87 dB VS– – 0.2 VS– V A
TA = –40°C to +125°C, CMRR > 87 dB VS– – 0.2 VS– B
Common-mode input high TA = 25°C, CMRR > 87 dB VS+ – 1.2 VS+ – 1.1 V A
TA = –40°C to +125°C, CMRR > 87 dB VS+ – 1.2 VS+ – 1.1 B
Common-mode rejection ratio 90 116 dB A
Input impedance differential mode 200 || 1 kΩ || pF C
OUTPUT
Single-ended output voltage: low TA = 25°C VS– + 0.06 VS– + 0.2 V A
TA = –40°C to +125°C VS– + 0.06 VS– + 0.2 B
Single-ended output voltage: high TA = 25°C VS+ – 0.2 VS+ – 0.11 V A
TA = –40°C to +125°C VS+ – 0.2 VS+ – 0.11 B
Output saturation voltage: high/low 110/60 mV C
Linear output current drive TA = 25°C, RL = 6 Ω ±15 ±22 mA A
TA = –40°C to +125°C ±15 B
POWER SUPPLY
Specified operating voltage 2.5 2.7 5.5 V B
Quiescent operating current/ch TA = 25°C, PD = VS+ 230 330 µA A
TA = –40°C to +125°C, PD = VS+ 270 370 B
Power-supply rejection (PSRR) 87 108 dB A
POWER DOWN
Enable voltage threshold Specified on above 2.1 V 2.1 V A
Disable voltage threshold Specified off below 0.7 V 0.7 V A
Disable pin bias current PD = VS– + 0.5 V 50 500 nA A
Power-down quiescent current PD = VS– + 0.5 V 0.5 2 µA A
Turnon time delay Time from PD = high to VOUT = 90% of final value, RL= 200 Ω 650 ns C
Turnoff time delay Time from PD = low to VOUT = 10% of original value, RL= 200 Ω 20 ns C
OUTPUT COMMON-MODE VOLTAGE CONTROL (VOCM)
Small-signal bandwidth VOCM input = 100 mVPP 23 MHz C
Slew rate VOCM input = 1 VSTEP 14 V/µs C
Gain 0.99 0.996 1.01 V/V A
Common-mode offset voltage Offset = output common-mode voltage – VOCM input voltage –5 ±1 5 mV A
VOCM input bias current VOCM = (VS+ + VS–)/2 –100 ±20 100 nA A
VOCM input voltage range 0.8 0.75 to 1.9 1.75 V A
VOCM input impedance 100 || 1.6 kΩ || pF C
Default voltage offset from
(VS+ + VS–)/2		 Offset = output common-mode voltage – (VS+ + VS–)/2 with VOCM input floating –10 ±3 10 mV A
(1) Positive current is out of the device inputs.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.