ZHCSJJ3E July   2009  – April 2019 TCA9555

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 5-V Tolerant I/O Ports
      2. 9.3.2 Hardware Address Pins
      3. 9.3.3 Interrupt (INT) Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Powered-Up
    5. 9.5 Programming
      1. 9.5.1 I/O Port
      2. 9.5.2 I2C Interface
        1. 9.5.2.1 Bus Transactions
          1. 9.5.2.1.1 Writes
          2. 9.5.2.1.2 Reads
      3. 9.5.3 Device Address
      4. 9.5.4 Control Register and Command Byte
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculating Junction Temperature and Power Dissipation
        2. 10.2.2.2 Minimizing ICC When I/O Is Used to Control LED
        3. 10.2.2.3 Pull-Up Resistor Calculation
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.6.1 Register Descriptions

The Input Port registers (registers 0 and 1) shown in Table 4 reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next.

Table 4. Registers 0 and 1 (Input Port Registers)

Bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default X X X X X X X X
Bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default X X X X X X X X

The Output Port registers (registers 2 and 3) shown in Table 5 show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Table 5. Registers 2 and 3 (Output Port Registers)

Bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 1 1 1 1 1 1 1 1
Bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 1 1 1 1 1 1 1 1

The Polarity Inversion registers (registers 4 and 5) shown in Table 6 allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Table 6. Registers 4 and 5 (Polarity Inversion Registers)

Bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 0 0 0 0 0 0 0 0
Bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 0 0 0 0 0 0 0 0

The Configuration registers (registers 6 and 7) shown in Table 7 configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

Table 7. Registers 6 and 7 (Configuration Registers)

Bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 1 1 1 1 1 1 1 1
Bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 1 1 1 1 1 1 1 1