8.3.1 Implementing the EN Signal

The SN75DP126 EN input gives control over the device reset and to place the device into Shutdown mode. When EN is low, all DPCD and local I²C registers are reset to their default values, and all Main Link lanes are disabled.

It is critical to reset the digital logic of the SN75DP126 after the V_CC supply (and V_DD supply for SN75DP126DS) is stable (that is, the power supply has reached the minimum recommended operating voltage). To reset the digital logic, transition the EN input from a low level to a high level. This method is shown in Figure 22. A system may provide a control signal to the EN signal that transitions low to high after the power supply is (or supplies are) stable. An alternate implementation is to use an external capacitor connected between EN and GND to allow delaying the EN signal during power up, as shown in Figure 23.

Figure 22. EN Input from Active Controller

Figure 23. External Capacitor Controlled EN

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Refer to the latest reference schematic for the SN75DP126 device and/or consider approximately 200nF capacitor as a reasonable first estimate for the size of the external capacitor.

When implementing an EN input from an active controller, it is recommended to use an open drain driver if the EN input is driven. This protects the EN input from damage of an input voltage greater than V_{DD_DREG} (or V_DD).

8.3.2 Hot Plug Detect (HPD) and Cable Adapter Detect (CAD) Description

The SN75DP126 drives the source-side Hot Plug Detect (HPD_SRC) signal output high to indicate to the GPU or graphics source that at least one sink has been detected and selected for connectivity; when no sink is selected the HPD_SRC is driven low. A high-level DP_HPD_SNK input indicates a DisplayPort sink device is connected, and a high-level TMDS_HPD_SNK input indicates a HDMI/DVI sink device is connected.

When DP_HPD_SNK is high, the DisplayPort sink is selected if the TMDS_HPD_SNK input is low. When TMDS_HPD_SNK is high, the HDMI/DVI sink is selected if the DP_HPD_SNK input is low. If both DP_HPD_SNK and TMDS_HPD_SNK inputs are high, then the PRIORITY input determines which sink is selected.

When the DisplayPort sink is selected, the CAD_SNK input indicates whether a DP sink (CAD_SNK = low) or a TMDS sink (CAD_SNK = high) is connected. The level of CAD_SNK is passed to the CAD_SRC output when the DisplayPort sink is selected. When the HDMI/DVI sink is selected, the CAD_SRC output is driven high regardless of the value input on CAD_SRC.

A sink is determined to be disconnected when the corresponding HPD_SNK input goes low for a duration of t_T(HPD). When switching from one sink to the other based on the PRIORITY selection, that is, both sinks are connected and either PRIORITY has changed or the sink with higher PRIORITY was connected after the sink with lower PRIORITY, the SN75DP126 asserts HPD_SRC for a duration at least t_T(HPD) before the switchover connection is established.

Through the local I²C interface it is possible to force the device to ignore DP_HPD_SNK, TMDS_HPD_SNK, and CAD_SNK, and control HPD_SRC and CAD_SRC directly.

When the EN pin is de-asserted (device is in power down mode), the HPD path from DP_HPD_SNK and/or TMDS_HPD_SNK to HPD_SRC is not reset. As a result, the source may need to retrain the link once EN is asserted (device is in active mode).

See Figure 10 and Table 1 for more information about the HPD and CAD functions.

8.3.3 OVS Function Description

The SN75DP126 provides an output-voltage select (OVS) control for the source side buffers on the DDC I²C lines. When the sink side is driven low, the corresponding source side driver turns on and drives the source side down to a low-level output voltage, V_OL. The value of V_OL and V_IL on the source side of the SN75DP126 depends on setting of the OVS pin. V_OL is always higher than V_IL on the source side to prevent lockup of the buffers on the DDC I²C lines. When the sink side is pulled up, the source side driver turns off and the sink side pin is high-impedance.

When the source side is driven below V_IL by an external I²C driver, both the sink and source side drivers are turned on. The sink side driver drives the sink side to near 0V, and the source side driver is on, but is overridden by the external I²C driver. When the source side is released by the external I²C driver, the source side driver is still on, so the source side is only able to rise to V_OL. However, the sink side driver turns off because the source side is above the V_IL threshold. If no external I²C driver is keeping the sink side low, the sink side rises causing the source side driver to turn off. See Figure 13 and Figure 14 for more information.

It is important that any external I²C driver on the source side is able to drive the bus below V_IL to achieve full operation. If the source side cannot be driven below V_IL, the sink side driver may not recognize and transmit the low value to the sink side.

8.3.4 AUX and DDC Configuration Details

The SN75DP126 connectivity between source-side AUX and DDC channels and the sink-side AUX and DDC channels is described in Table 3. Refer to the BLOCK DIAGRAM for more information about the AUX and DDC switches, buffers, and logic elements represented in Table 1.

Note that the DDC interface incorporates 60kΩ pull-up resistors on SDA_SRC and SCL_SRC which are enabled when CAD_SRC is driven high, and disabled (turned off) when CAD_SRC is driven low.

8.3.5 Source-Side Main Link EQ Configuration Details

A variety of EQ settings are available through external pin configuration to accommodate for different PCB loss and GPU settings. The I²C interface is utilized to fully customize EQ configuration, lane-by-lane, beyond the input pin configuration options, as described in Table 2.

8.3.6 DP-HDMI Adaptor ID Buffer

The SN75DP126 includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by the VESA DisplayPort Interoperability Guidelines Version 1.1a, accessible by standard I²C protocols through the DDC interface when the HDMI/DVI sink is selected. The DP-HDMI adapter buffer is accessed at target addresses 80h (Write) and 81h (Read).

The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters as illustrated in Table 3, and supports the Write command procedures (accessed at target address 80h) to select the sub-address, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist Version 1.0 section 2.3.

8.3.7 GPU with a Unified AUX/DDC Configuration

The SN75DP126 supports graphics processors with unified AUX/DDC configurations, where the source AUX channel is multiplexed with the source DDC channel, as illustrated in Figure 24.

Graphics processors with separate AUX and DDC channels (ie. non-unified) are also supported, where the separate channels are directly routed to the separate channels on the SN75DP126, maintaining the AC coupling on the AUX channel. In the non-unified configuration, it is recommended to implement 2-kΩ pull-up resistors on the source-side DDC channel. See Figure 25.

Figure 24. GPU with a Unified AUX/DDC Configuration

8.3.8 GPU with Separate DDC and AUX Channels

Graphics processors with separate AUX and DDC channels (ie. non-unified) are also supported, where the separate channels are directly routed to the separate channels on the SN75DP126, maintaining the AC coupling on the AUX channel. In the non-unified configuration, it is recommended to implement 2-kΩ pull-up resistors on the source-side DDC channel. See Figure 25.

Figure 25. GPU with Separate DDC and AUX Channels

8.4.1 Operating Modes Overview

Figure 26. SN75DP126 Operating Modes Flow Diagram

8.5.1 Link Training and DPCD Description

The SN75DP126 can monitor the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers during Link Training in DisplayPort mode, to select the output voltage swing V_OD, output pre-emphasis, and the EQ setting of the Main Link. The AUX monitor for SN75DP126 supports Link Training in 1-Mbps Manchester mode, and is disabled during TMDS modes of operation.

The DPCD registers monitored by SN75DP126 are listed below. Bit fields not listed are reserved and values written to reserved fields are ignored.

8.5.2 Local I²C Interface Overview

The SN75DP126 local I²C interface is enabled when EN is input high, and the I2C_CTL_EN control input is not input low. The SCL_CTL and SDA_CTL terminals are used for I²C clock and I²C data respectively. The SN75DP126 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the standard mode transfer up to 100 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN75DP126 is factory preset to 010110x with the least significant bit being determined by the I2C_CTL_EN 3-level control input. Table 6 clarifies the SN75DP126 target address.

The following procedure is followed to write to the SN75DP126 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SN75DP126 7-bit address and a zero-value “W/R” bit to indicate a write cycle
2. The SN75DP126 acknowledges the address cycle
3. The master presents the sub-address (I²C register within SN75DP126) to be written, consisting of one byte of data, MSB-first
4. The SN75DP126 acknowledges the sub-address cycle
5. The master presents the first byte of data to be written to the I²C register
6. The SN75DP126 acknowledges the byte transfer
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN75DP126
8. The master terminates the write operation by generating a stop condition (P)

The following procedure is followed to read the SN75DP126 I²C registers.

1. The master initiates a read operation by generating a start condition (S), followed by the SN75DP126 7-bit address and a one-value “W/R” bit to indicate a read cycle
2. The SN75DP126 acknowledges the address cycle
3. The SN75DP126 transmit the contents of the memory registers MSB-first starting at register 00h
4. The SN75DP126 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer
5. If an ACK is received, the SN75DP126 transmits the next byte of data
6. The master terminates the read operation by generating a stop condition (P)

Note that no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I²C master terminates the read operation.

Refer to Table 7 for SN75DP126 local I²C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.