SCES198N April   1999  – December 2015 SN74LVC2G08

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Specifications
    1. 3.1 Absolute Maximum Ratings
    2. 3.2 ESD Ratings
    3. 3.3 Thermal Information
    4. 3.4 Electrical Characteristics
    5. 3.5 Typical Characteristics
  4. 4Detailed Description
    1. 4.1 Overview
    2. 4.2 Functional Block Diagram
    3. 4.3 Feature Description
      1. 4.3.1 Down Voltage Translation
    4. 4.4 Device Functional Modes
  5. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Typical Application
      1. 5.2.1 Design Requirements
      2. 5.2.2 Detailed Design Procedure
      3. 5.2.3 Application Curves
  6. 6Power Supply Recommendations
  7. 7Layout
    1. 7.1 Layout Guidelines
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Community Resources
    2. 8.2 Trademarks
    3. 8.3 Electrostatic Discharge Caution
    4. 8.4 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

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7 Layout

7.1 Layout Guidelines

When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient.

7.2 Layout Example

SN74LVC2G08 layout_scls749.gif Figure 6. Layout Example