SCES305M January   2001  – August 2026 SN74LVC1G240

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics: –40°C to 85°C, CL = 15pF
    7. 5.7 Switching Characteristics: –40°C to 85°C
    8. 5.8 Switching Characteristics: –40°C to 125°C
    9. 5.9 Operating Characteristics
  8. 6 Parameter Measurement Information
  9.   18
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
      5. 7.3.5 Over-Voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Application Curves
      1. 8.3.1 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Description

The SN74LVC1G240 device is a single inverter with 3-state output. The output is disabled when the output-enable (OE) input is high. To retain high-impedance during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74LVC1G240
DBV (SOT-23, 5) 2.9mm × 2.8mm 2.9mm × 1.6mm
DCK (SC70, 5) 2mm × 2.1mm 2mm × 1.25mm
DRY (SON, 6) 1.45mm × 1mm 1.45mm × 1mm
YZP (DSBGA, 5) 1.39mm × 0.89mm 1.39mm × 0.89mm
DSF (SON, 6) 1mm × 1mm 1mm × 1mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LVC1G240 Logic Diagram Logic Diagram