SCES305M January   2001  – August 2026 SN74LVC1G240

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics: –40°C to 85°C, CL = 15pF
    7. 5.7 Switching Characteristics: –40°C to 85°C
    8. 5.8 Switching Characteristics: –40°C to 125°C
    9. 5.9 Operating Characteristics
  8. 6 Parameter Measurement Information
  9.   18
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
      5. 7.3.5 Over-Voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Application Curves
      1. 8.3.1 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13. 10Revision History
  14. 11Mechanical, Packaging, and Orderable Information

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10 Revision History

Changes from December 1, 2013 to August 12, 2026 (from Revision L (December 2013) to Revision M (August 2026))

  • Updated Device Information table to include body and package dimensionsGo
  • Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Added Device Information table.Go
  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Moved Tstg to Absolute Maximum Ratings table.Go
  • Added Thermal Information tableGo
  • Changed Junction-to-ambient thermal resistance value for DBV package from: 206°C/W to: 357.1°C/WGo
  • Changed Junction-to-ambient thermal resistance value for DCK package from: 252°C/W to: 371°C/WGo
  • Updated Overview, Application and Implementation, Device and Documentation Support sections to extend detailed feature descriptions and more detailed information. Go
  • Added parallel trace spacing recommendation to layout guidelines. Changed wording of "Avoid branches; buffer signals that must branch separately" to "Avoid branches; buffer each signal that must branch separately"Go

Changes from Revision K (March 2012) to Revision L (December 2013)

  • Updated document to new TI data sheet format.Go
  • Removed Ordering Information table.Go
  • Updated operating temperature range.Go