ZHCSUM6R January 2015 – February 2024 SN74LVC125A
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The SN74LVC125A device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.