ZHCSS51G june 1998 – may 2023 SN74AHCT174
PRODMIX
请参考 PDF 数据表获取器件具体的封装图。
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.