ZHCSL88 October   2020 SN65HVD64

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Coaxial Interface
      2. 8.3.2 Reference Input
      3. 8.3.3 RS-485 Direction Control
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driver Amplitude Adjust
      2. 9.1.2 Direction Control
      3. 9.1.3 Direction Control Time Constant
      4. 9.1.4 Conversion Between dBm and Peak-to-Peak Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

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6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current DIRSET1 = L
DIRSET2 = H		 TXIN = L (active) 28 33 mA
TXIN = H (quiescent) 25 31
TXIN = 115 kbps,
50% duty cycle		 27 33
DIRSET1 = H, DIRSET2 = H (standby) 12 17
IVL Logic supply current TXIN = H, RXIN = DC input 50 µA
PSRR Receiver power supply rejection ratio VTXIN = VL 45 60 dB
TSD_RISE Thermal shutdown rising 143 156 170 °C
TSD_FALL Thermal shutdown falling 123 136 147 °C
TSD_HYS Thermal shutdown hysteresis 18 20 23 °C
LOGIC PINS
VOH High-level logic output voltage
(RXOUT, DIR)		 IOH = –4 mA for VL > 2.4 V,
IOH = –2 mA for VL < 2.4 V		 90%VVL V
VOL Low-level logic output voltage
(RXOUT, DIR)		 IOL = 4 mA for VL > 2.4 V,
IOL = 2 mA for VL < 2.4 V		 10%VVL V
COAX DRIVER
VO(PP) Peak-to-peak output voltage at device pin TXOUT
(see Figure 7-1)		 VRES = 1.5 V (Maximum setting) 2.24 2.5 VPP
VRES = 0.7 V (Minimum setting) 1.17 1.3
VO(PP) Peak-to-peak voltage at coax out
(see Figure 7-1)		 VRES = 1.5 V 5 6 dBm
VRES = 0.7 V –0.6 0.3
VO(OFF) Off-state output voltage At TXOUT 1 mVpp
At coax out –60 dBm
Output emissions Coupled to coaxial cable with characteristic impedance of 50 Ω, as shown in Figure 6-1(1)(2) N/A
fO Output frequency 2.176 MHz
∆f Output frequency variation –100 100 ppm
ZO Output impedance At 100 kHz 0.03 Ω
At 10 MHz 3.5
| IOS | Short-circuit output current TXOUT is also protected by a thermal shutdown circuit during short-circuit faults 300 450 mA
COAX RECEIVER
VIT Input threshold fIN = 2.176 MHz 79 112 158 mVPP
–18 –15 –12 dBm
ZIN Input impedance f = fO 11 21 kΩ
RECEIVER FILTER
fPB Passband VRXIN = 1.12VP_P 1.1 4.17 MHz
fREJ Receiver rejection range 2.176-MHz carrier amplitude of 112.4 mVPP, frequency band of spurious components with 800 mVPP allowed. 1.1 4.17 MHz
tnoise filter Receiver noise filter time (slow bit rate) DIRSET for 9.6 kbps 4 µs
Receiver noise filter time (fast bit rate) DIRSET for > 9.6 kbps 2 µs
XTAL AND SYNC
II Input leakage current XTAL1, XTAL2, 0V < VIN < VCC –15 15 µA
VOL Output low voltage SYNCOUT, with 1-kΩ resistor from SYNCOUT to VCC 0.4 V
(1) Specified by design with a recommended 470-pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup.
(2) Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 7-3.