SBOS392I August   2007  – April 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Thermal Hysteresis
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up Time
      2. 8.3.2 Low Temperature Drift
      3. 8.3.3 Power Dissipation
      4. 8.3.4 Noise Performance
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 REF3312 in a Bipolar Signal-Chain Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Op Amp Level-Shift Design
          2. 9.2.1.2.2 Differential Input Attenuator Design
          3. 9.2.1.2.3 Input Filtering
          4. 9.2.1.2.4 Component Selection
            1. 9.2.1.2.4.1 Voltage References
            2. 9.2.1.2.4.2 Op Amp
          5. 9.2.1.2.5 Input Attenuation and Level Shifting
          6. 9.2.1.2.6 Input Filtering
          7. 9.2.1.2.7 Passive Component Tolerances and Materials
        3. 9.2.1.3 Application Curves
          1. 9.2.1.3.1 DC Performance
          2. 9.2.1.3.2 AC Performance
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.1.2.5 Input Attenuation and Level Shifting

For this design, the bipolar ±5V input must be attenuated and level shifted so the differential voltage is within the input range of ±VREF / 2, or ±0.625V. The accuracy of the op amp output and ADC input can degrade near the supply rails and VREF voltage, so the output is designed to produce a 0.125V to 1.125V output, or ±0.5V for a ±5V input. Scaling the output this way also increases the allowable input range to ±6V, and allows for some underscale and overscale voltage measurement and protection.

Use Equation 13 to scale the ±5V input to a ±0.5V differential voltage, as shown in Equation 16.

Equation 16. 0.5 V = R 2 2 × 100 k Ω × 5 V

where

  • R1 = R4 = 100kΩ

R1 and R4 dominate the input impedance for this design and are therefore selected to be 100kΩ. Higher values can be selected to increase the input impedance at the expense of input noise.

With the value for R2 and R3 selected as 20kΩ, the value for R5 is calculated, as shown in Equation 17:

Equation 17. R 5 = R 2 2 × 10 k Ω

where

  • R2 = R3 = 20kΩ

For A1– to equal to VREF / 2, R6 must equal R7. Two 47kΩ resistors are used to conserve power without creating an impedance too weak to drive the ADC input.