SBOS223G December   2001  – August 2016 OPA690

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Electrical Characteristics: VS = 5 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 Typical Characteristics: VS = ±5 V
      2. 7.7.2 Typical Characteristics: 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wideband Voltage-Feedback Operation
      2. 8.3.2 Bandwidth Versus Gain: Noninverting Operation
      3. 8.3.3 Inverting Amplifier Operation
      4. 8.3.4 Output Current and Voltage
      5. 8.3.5 Driving Capacitive Loads
      6. 8.3.6 Distortion Performance
      7. 8.3.7 Noise Performance
      8. 8.3.8 DC Accuracy and Offset Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Optimizing Resistor Values
      2. 9.1.2 Thermal Analysis
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply ADC Interface
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Single-Supply Active Filters
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
      3. 9.2.3 High-Performance DAC Transimpedance Amplifier
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 High-Power Line Driver
        1. 9.2.4.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Input and ESD Protection
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Macromodels and Applications Support
      2. 12.1.2 Demonstration Fixtures
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Optimizing Resistor Values

Because the OPA690 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection must be made with a 25-Ω resistor, not a direct short. This isolates the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 applications, the feedback resistor value must be between 200 Ω and 1.5 kΩ. Below 200 Ω, the feedback network presents additional output loading which can degrade the harmonic distortion performance of the OPA690. Above 1.5 kΩ, the typical parasitic capacitance (approximately 0.2 pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response.

A good rule of thumb is to target the parallel combination of RF and RG (see Figure 36) to be less than approximately 300 Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2-pF total parasitic on the inverting node, holding RF || RG < 300 Ω keeps this pole above 250 MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.

9.1.2 Thermal Analysis

Due to the high output power capability of the OPA690, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case must the maximum junction temperature be allowed to exceed 175°C.

Operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies) under the condition in Equation 3.

Equation 3. PDL = VS2/(4 × RL)

where

  • RL includes feedback network loading

NOTE

It is the power in the output stage and not into the load that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using an OPA690-DBV (6-pin SOT-23 package) in the circuit of Figure 36 operating at the maximum specified ambient temperature of 85°C and driving a grounded
20-Ω load.

Equation 4. PD = 10 V × 6.2 mA + 52/(4 × (20 Ω || 804 Ω)) = 382 mW
Equation 5. Maximum TJ = 85°C + (0.38 W × 150°C/W) = 142°C

Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. The highest possible internal dissipation occurs if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. Figure 19, the output V-I plot shown in Typical Characteristics: VS = ±5 V, include a boundary for 1-W maximum internal power dissipation under these conditions.

9.2 Typical Applications

9.2.1 Single-Supply ADC Interface

OPA690 ai_sfdr_test_cir_bos223.gif Figure 45. SFDR vs IB Test Circuit

9.2.1.1 Design Requirements

Most modern, high performance ADCs (such as the TI ADS8xx and ADS9xx series) operate on a single 5-V (or lower) power supply. It is a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5 MHz. The high slew rate, exceptional output swing, and high linearity of the OPA690 make it an ideal single-supply ADC driver.

9.2.1.2 Detailed Design Procedure

The Single-Supply ADC Driver shows one possible (inverting) interface. Figure 45 shows the test circuit of Figure 37 modified for a capacitive (ADC) load and with an optional output pulldown resistor (RB).

The OPA690 in the circuit of Figure 45 provides > 200-MHz bandwidth for a 2-VPP output swing. Minimal 3rd-harmonic distortion or two-tone, 3rd-order intermodulation distortion is observed due to the very low crossover distortion in the OPA690 output stage. The limit of output spurious-free dynamic range (SFDR) is set by the 2nd-harmonic distortion. Without RB, the circuit of Figure 45 measured at 10 MHz shows an SFDR of
57 dBc. This may be improved by pulling additional DC bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5 V for Figure 45). Adjusting IB gives the improvement in SFDR shown in Figure 46. SFDR improvement is achieved for IB values up to 5 mA, with worse performance for higher values.

9.2.1.3 Application Curve

OPA690 ai_sfdr-ib_bos223.gif Figure 46. SFDR vs IB

9.2.2 Single-Supply Active Filters

OPA690 ai_active_filter_1_bos223.gif Figure 47. Single-Supply, High-Frequency Active Filter

9.2.2.1 Design Requirements

The high bandwidth provided by the OPA690, while operating on a single 5-V supply, lends itself well to high-frequency active filter designs. Again, the key additional requirement is to establish the DC operating point of the signal near the supply midpoint for highest dynamic range. See Figure 47 for an example design of a 5-MHz low-pass Butterworth filter using the Sallen-Key topology.

Both the input signal and the gain setting resistor are AC-coupled using 0.1-µF blocking capacitors (actually giving band-pass response with the low-frequency pole set to 32 kHz for the component values shown). As discussed for Figure 37, this allows the midpoint bias formed by the two 1.87-kΩ resistors to appear at both the input and output pins. The midband signal gain is set to 4 (12 dB) in this case. The capacitor to ground on the noninverting input is intentionally set larger to dominate input parasitic terms. At a gain of 4, the OPA690 on a single supply shows approximately 80-MHz small- and large-signal bandwidth. The resistor values have been slightly adjusted to account for this limited bandwidth in the amplifier stage. Tests of this circuit show a precise 5-MHz, −3-dB point with a maximally flat pass band (above the 32-kHz AC-coupling corner), and a maximum stop band attenuation of 36 dB at the −3-dB bandwidth of 80 MHz of the amplifier.

9.2.2.2 Application Curve

OPA690 ai_active_filter_2_bos223.gif Figure 48. 5-MHz, 2nd-Order Butterworth Filter Response

9.2.3 High-Performance DAC Transimpedance Amplifier

OPA690 ai_dac_trans_amp_bos223.gif Figure 49. DAC Transimpedance Amplifier

9.2.3.1 Design Requirements

High-frequency, direct digital synthesis (DDS) Digital-to-Analog Converters (DACs) require a low-distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 49 for a single-ended output drive implementation.

9.2.3.2 Detailed Design Procedure

In this circuit, only one side of the complementary output drive signal is used. Figure 49 shows the signal output current connected into the virtual ground summing junction of the OPA690, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA690. The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance produces a zero in the noise gain for the OPA690 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in the feedback network must be set to Equation 6.

Equation 6. OPA690 q_2p_rf_cf_bos223.gif

Equation 6 gives a closed-loop transimpedance bandwidth, f−3dB, of approximately Equation 7.

Equation 7. OPA690 q_f3db_bos223.gif

where

  • GBP = gain bandwidth product (Hz) for the OPA690

9.2.4 High-Power Line Driver

OPA690 ai_coax_driver_bos223.gif Figure 50. High-Power Coax Line Driver

9.2.4.1 Design Requirements

The large output swing capability of the OPA690 and its high current capability allow it to drive a 50-Ω line with a peak-to-peak signal up to 4 VPP at the load, or 8 VPP at the output of the amplifier using a single 12-V supply. Figure 50 shows such a circuit set for a gain of 8 to the output or 4 to the load.

The 5-pF capacitor in the feedback loop provides added bandwidth control for the signal path.