ZHCSNC5A February   2021  – April 2021 OPA2607-Q1 , OPA607-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).

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Figure 7-1 Open Loop Gain and Phase vs Frequency
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Figure 7-3 Input Current Noise Density vs Frequency
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VOUT = 20 mVPP
Figure 7-5 Small-Signal Frequency Response vs Capacitive Load
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Figure 7-7 Large-Signal Frequency Response vs Output Voltage
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VOUT = 2 VPP
Figure 7-9 Harmonic Distortion vs Frequency
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Figure 7-11 Rejection Ratio vs frequency
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Figure 7-13 Output Overdrive Recovery
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TRISE = TFALL = 40 nsec
Figure 7-15 Small-Signal Transient Response
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Simulated
Figure 7-17 Step Settling Time
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VOUT = 200 mVPP
Figure 7-19 Overshoot vs Capacitive Load
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32 Units, Normalized to
VOS = 0V at 25°C
Figure 7-21 Input Offset Voltage vs Temperature
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VS = ±2.75 V
Figure 7-23 Input Offset vs Common Mode Voltage
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Figure 7-25 Common Mode Rejection Ratio vs Temperature
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Figure 7-27 Input Bias and Offset Current vs Temperature
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Figure 7-29 Output Voltage vs Output Current Sourcing and Sinking
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Figure 7-31 Crosstalk vs Frequency
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Figure 7-2 Input Voltage Noise Density vs Frequency
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VOUT = 20 mVPP
Figure 7-4 Small-Signal Frequency Response vs Gain
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VOUT = 20 mVPP
Figure 7-6 Small-Signal Frequency Response vs Output Load
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Figure 7-8 Large-Signal Response Flatness vs Frequency
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Frequency = 20 kHz
Figure 7-10 Harmonic Distortion vs Output Voltage
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Figure 7-12 Open Loop Output Impedance vs Frequency
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TRISE = 1 µsec , TFALL = 0.7 µsec
Figure 7-14 Large-Signal Transient Response
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Figure 7-16 Phase Margin vs Capacitive Load
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Figure 7-18 Recommended Isolation Resistor vs Capacitive Load
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9000 units
Figure 7-20 Input Offset Voltage Distribution
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32 Units, –40°C to +125°C
Figure 7-22 Input Offset Drift Distribution
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32 Units
Figure 7-24 Input Offset vs Supply
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Figure 7-26 Short-Circuit Current vs Temperature
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Figure 7-28 Quiescent Current vs Temperature
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Figure 7-30 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency