ZHCSMD4C January   2022  – December 2022 OPA593

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Overcurrent Flag
      3. 7.3.3 Overtemperature Flag
      4. 7.3.4 Output Enable and Disable
      5. 7.3.5 Mux-Friendly Inputs
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Output Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High Voltage 2:1 Multiplexer With Unity Gain
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ 仿真软件（免费下载）
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.6 Typical Characteristics

at TA = 25°C, VS = (V+) − (V−) = 85 V, ILIMIT = 100 mA, VCM = VOUT = VS/2, and RL = 10 kΩ connected to VS/2 (unless otherwise noted)

VS = 85 V, 160 typical units
Figure 6-1 Input Offset Production Distribution
TA = −40ºC, 30 typical units
Figure 6-3 Input Offset Production Distribution
TA = –40ºC to +125ºC
Figure 6-5 Input Offset Voltage Drift Distribution
 
Figure 6-7 Input Offset Voltage vs Common-Mode Voltage
5 typical units
Figure 6-9 Input Offset Voltage vs Temperature
 
Figure 6-11 PSRR vs Temperature
 
Figure 6-13 Input Bias Current and Current Offset vs Temperature
 
Figure 6-15 Open-Loop Gain and Phase vs Frequency
 
Figure 6-17 Closed-Loop Gain vs Frequency
VS = 8 V, ILIMIT = 100 mA
Figure 6-19 Output Voltage vs Output Sourcing Current
VS = 48 V, ILIMIT = 100 mA
Figure 6-21 Output Voltage vs Output Sourcing Current
VS = 85 V, ILIMIT = 100 mA
Figure 6-23 Output Voltage vs Output Sourcing Current
VS = 8 V, ILIMIT = 250 mA
Figure 6-25 Output Voltage vs Output Sourcing Current
VS = 48 V, ILIMIT = 250 mA
Figure 6-27 Output Voltage vs Output Sourcing Current
VS = 85 V, ILIMIT = 250 mA
Figure 6-29 Output Voltage vs Output Sourcing Current
VS = 8 V, RL = 10 Ω to mid-supply
Figure 6-31 Output Voltage vs Current Limit Set
VS = 85 V, RL = 10 Ω to mid-supply
Figure 6-33 Output Voltage vs Output Sourcing Current
VS = 8 V, RL = 10 Ω to mid-supply 
Figure 6-35 Output Sourcing Current Error vs Current Limit Set
VS = 85 V, RL = 10 Ω to mid-supply
Figure 6-37 Output Sourcing Current Error vs Current Limit Set
ILIMIT = 100 mA
Figure 6-39 Short Circuit Current vs Temperature
 
Figure 6-41 Open-Loop Output Impedance vs Frequency
 
Figure 6-43 Input Voltage Noise Spectral Density
VOUT = 3 VRMS 
Figure 6-45 Total Harmonic Distortion + Noise vs Frequency
 Gain = 10 V/V, VOUT = 15 VRMS 
Figure 6-47 Total Harmonic Distortion + Noise vs Frequency
 
Figure 6-49 EMIRR vs Frequency
Gain = 10 V/V
Figure 6-51 Phase Margin vs Capacitive Load
 Gain = −1 V/V
Figure 6-53 Small-Signal Overshoot vs Capacitive Load
10-mV step, f = 100 kHz, gain = −1 V/V
Figure 6-55 Small-Signal Step Response
10-mV step, f = 1 MHz, gain = −1 V/V
Figure 6-57 Small-Signal Step Response
10-V step, f = 100 kHz, gain = −1 V/V
Figure 6-59 Large-Signal Step Response
70-V step, f = 100 kHz, gain = −1 V/V
Figure 6-61 Large-Signal Step Response
 Gain = −10 V/V
Figure 6-63 Positive Overload Recovery
5 typical units 
Figure 6-65 Quiescent Current vs Supply Voltage
 
Figure 6-67 Quiescent Current vs Enable Voltage
VE/D = 5 V
Figure 6-69 Enable/Disable Pin Current vs Temperature
 
Figure 6-71 Enable Response
 E/D Com = 0 V
Figure 6-73 Overtemperature Flag Pin Voltage vs Temperature
VS = 8 V, 160 typical units
Figure 6-2 Input Offset Production Distribution
TA = 125ºC, 30 typical units
Figure 6-4 Input Offset Production Distribution
360 typical units
Figure 6-6 Input Bias Current Production Distribution
5 typical units
Figure 6-8 Input Offset Voltage vs Supply Voltage
 
Figure 6-10 CMRR vs Temperature
 
Figure 6-12 Input Bias Current vs Common-Mode Voltage
 
Figure 6-14 PSRR and CMRR vs Frequency
 
Figure 6-16 Open Loop Gain vs Temperature
 
Figure 6-18 Maximum Output Voltage vs Frequency
VS = 8 V, ILIMIT = 100 mA
Figure 6-20 Output Voltage vs Output Sinking Current
VS = 48 V, ILIMIT = 100 mA
Figure 6-22 Output Voltage vs Output Sinking Current
VS = 85 V, ILIMIT = 100 mA
Figure 6-24 Output Voltage vs Output Sinking Current
VS = 8 V, ILIMIT = 250 mA
Figure 6-26 Output Voltage vs Output Sinking Current
VS = 48 V, ILIMIT = 250 mA
Figure 6-28 Output Voltage vs Output Sinking Current
VS = 85 V, ILIMIT = 250 mA
Figure 6-30 Output Voltage vs Output Sinking Current
VS = 8 V, RL = 10 Ω to mid-supply
Figure 6-32 Output Voltage vs Current Limit Set
VS = 85 V, RL = 10 Ω to mid-supply
Figure 6-34 Output Voltage vs Output Sinking Current
 VS = 8 V, RL = 10 Ω to mid-supply
Figure 6-36 Output Sinking Current Error vs Current Limit Set
VS = 85 V, RL = 10 Ω to mid-supply
Figure 6-38 Output Sinking Current Error vs Current Limit Set
ILIMIT = 250 mA
Figure 6-40 Short Circuit Current vs Temperature
 
Figure 6-42 0.1-Hz to 10-Hz Noise
 
Figure 6-44 Input Current Noise Spectral Density
VOUT = 3 VRMS 
Figure 6-46 Total Harmonic Distortion + Noise vs Amplitude
Gain = 10 V/V, VOUT = 15 VRMS 
Figure 6-48 Total Harmonic Distortion + Noise vs Amplitude
 
Figure 6-50 No Phase Reversal
Gain = 1 V/V
Figure 6-52 Small-Signal Overshoot vs Capacitive Load
10-mV step, f = 100 kHz, gain = 1 V/V
Figure 6-54 Small-Signal Step Response
10-mV step, f = 1 MHz, gain = 1 V/V
Figure 6-56 Small-Signal Step Response
10-V step, f = 100 kHz, gain = 1 V/V
Figure 6-58 Large-Signal Step Response
70-V step, f = 100 kHz, gain = 1 V/V
Figure 6-60 Large-Signal Step Response
 12-bit settling (0.01%), 70-V step
Figure 6-62 Settling Time
 Gain = −10 V/V
Figure 6-64 Negative Overload Recovery
 
Figure 6-66 Quiescent Current Temperature Response
ILIMIT = 100 mA
Figure 6-68 Current Limit Response
 
Figure 6-70 Enable Pin Current vs Enable Pin Voltage
 Flag is asserted
Figure 6-72 Current-Limit Flag Pin vs Current-Limit Flag Pin Voltage
Flag is asserted
Figure 6-74 Overtemperature Flag Pin Current vs Overtemperature Flag Pin Voltage