ZHCSLZ5D October   2020  – December 2023 OPA3S328

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagram
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switch Characterization Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Operating Voltage
      2. 7.3.2 Input and ESD Protection
      3. 7.3.3 Programmable Switches
      4. 7.3.4 Rail-to-Rail Input
      5. 7.3.5 Phase Reversal
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Capacitive Load and Stability
      2. 8.1.2 EMI Susceptibility and Input Filtering
      3. 8.1.3 Transimpedance Amplifier
        1. 8.1.3.1 Optimizing the Transimpedance Circuit
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ 仿真软件（免费下载）
        3. 9.1.1.3 TI 参考设计
        4. 9.1.1.4 滤波器设计工具
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

4 Pin Configuration and Functions

GUID-20210917-CA0I-D39F-7FL3-7WJBGHPZM24F-low.svgFigure 4-1 RGR Package, 20-Pin VQFN (Top View)
GUID-20210914-CA0I-K7TF-DQX5-D3WQVKSHT6VF-low.svgFigure 4-2 YBJ Package, 24-Pin DSBGA (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
RGR (VQFN) YBJ (DSBGA)
DNC — B4, C4, D4 — Do not connect
GND 3 C5 Ground Digital ground pin
–INA 18 A1 Input Negative (inverting) input for amplifier A
–INB 8 E1 Input Negative (inverting) input for amplifier B
+INA 17 A3 Input Positive (noninverting) input for amplifier A
+INB 9 E3 Input Positive (noninverting) input for amplifier B
INSA 16 B2 Input/Output Switch A1, A2, A3 input
INSB 10 D2 Input/Output Switch B1, B2, B3 input
OUTA 19 A2 Output Output of amplifier A
OUTB 7 E2 Output Output of amplifier B
OUTSA1 14 C1 Input/Output Switch A1 output
OUTSA2 15 B1 Input/Output Switch A2 output
OUTSA3 — B3 Input/Output Switch A3 output
OUTSB1 13 C2 Input/Output Switch B1 output
OUTSB2 12 D1 Input/Output Switch B2 output
OUTSB3 11 D3 Input/Output Switch B3 output
SELA0 2 B5 Input Input select for switch matrix A
SELA1 1 A4 Input Input select for switch matrix A
SELB0 4 D5 Input Input select for switch matrix B
SELB1 5 E4 Input Input select for switch matrix B
V– 6 E5 Power Negative (lowest) power supply
V+ 20 A5 Power Positive (highest) power supply
Thermal Pad Thermal Pad — — Exposed thermal pad. Connect to V–
Table 4-2 Select Pin Decoder
SELA1 SELA0 SELB1 SELB0 SHUTDOWN STATUS SWITCH CONFIGURATION
SWITCH A1 STATUS SWITCH A2 STATUS SWITCH A3(1) STATUS SWITCH B1 STATUS SWITCH B2 STATUS SWITCH B3 STATUS
LOW LOW — — Amplifier A enabled CLOSED OPEN OPEN — — —
LOW HIGH — — Amplifier A enabled OPEN CLOSED OPEN — — —
HIGH LOW — — Amplifier A enabled OPEN OPEN CLOSED — — —
HIGH HIGH — — In special mode, the SELB0 and SELB1 decoding scheme shown here is ignored, and instead, Table 4-3 applies. — — —
— — LOW LOW Amplifier B enabled — — — CLOSED OPEN OPEN
— — LOW HIGH Amplifier B enabled — — — OPEN CLOSED OPEN
— — HIGH LOW Amplifier B enabled — — — OPEN OPEN CLOSED
— — HIGH HIGH Amplifier B enabled — — — OPEN OPEN OPEN
(1) Switch A3 is available in the YBJ (DSBGA-24) package option only.
Table 4-3 Select Pin Decoder in Special Mode: SELA0 = SELA1 = HIGH
SELA1 SELA0 SELB1 SELB0 SHUTDOWN STATUS SWITCH CONFIGURATION
SWITCH A1 STATUS SWITCH A2 STATUS SWITCH A3(1) STATUS SWITCH B1 STATUS SWITCH B2 STATUS SWITCH B3 STATUS
HIGH HIGH LOW LOW Amplifier A in power down and amplifier B enabled OPEN OPEN OPEN OPEN OPEN OPEN
HIGH HIGH LOW HIGH Amplifier A enabled and amplifier B in power down OPEN OPEN OPEN OPEN OPEN OPEN
HIGH HIGH HIGH LOW Both Amplifier A and amplifier B enabled OPEN OPEN OPEN OPEN OPEN OPEN
HIGH HIGH HIGH HIGH Both Amplifier A and amplifier B in power down OPEN OPEN OPEN OPEN OPEN OPEN
(1) Switch A3 is available in the YBJ (DSBGA-24) package option only.