ZHCSOD6E December   2003  – August 2023 OPA1632

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations
        2. 8.4.1.2 Power Dissipation and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

at VS = ±15 V, RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input offset voltage ±0.5 ±3 mV
vs temperature, dc
 dVOS/dT ±2.5 μV/°C
vs power supply, dc PSRR 13 316 μV/V
INPUT BIAS CURRENT
Input bias current, IB  7.9 14 μA
Input offset current, IOS ±100 ±500 nA
NOISE
Input voltage noise f = 10 kHz 1.25 nV/√Hz
Input current noise f = 10 kHz 1.7 pA/√Hz
INPUT VOLTAGE
Common-mode input voltage  (V−) + 1.5 (V+) − 1 V
Common-mode rejection ratio, dc 74 90 dB
INPUT IMPEDANCE
Input impedance Measured into each input pin, common-mode 215 || 1.4 MΩ || pF
Measured into each input pin, differential 10 || 3.1 kΩ || pF
OPEN-LOOP GAIN
Open-loop gain, dc 66 78 dB
FREQUENCY RESPONSE
Small-signal bandwidth G = +1, RF= 348 Ω 180 MHz
VO = 100 mVPP, peaking < 0.5 dB G = +2,
RF = 602 Ω		 104
G = +5,
RF = 1.5 kΩ		 46
G = +10,
RF = 3.01 kΩ		 24
Bandwidth for 0.1-dB flatness G = +1, VO = 100 mVPP 40 MHz
Peaking at a gain of 1 VO = 100 mVPP 0.5 dB
Large-signal bandwidth G = +2, VO = 20 VPP 1.8 MHz
Slew rate (25% to 75%) G = +1 72 V/μs
Rise and fall time G = +1, VO = 5-V step
 69 ns
Settling time To 0.1% G = +1, VO = 2-V step 36 ns
To 0.01% G = +1, VO = 2-V step 49
Total harmonic distortion + noise
 Differential
input/output		 G = +1, f = 1 kHz, 
VO = 3 VRMS		 RL = 600 Ω 0.00003%
RL = 2 kΩ 0.000028%
Single-ended
in/differential out		 G = +1, f = 1 kHz, 
VO = 3 VRMS		 RL = 600 Ω 0.000036%
RL = 2 kΩ 0.000031%
Intermodulation distortion Differential
input/output		 G = +1, SMPTE/DIN, VO = 2 VPP RL = 600 Ω 0.000061%
RL = 2 kΩ 0.000061%
Single-ended
in/differential out		 G = +1, SMPTE/DIN, VO = 2 VPP RL = 600 Ω 0.000073%
RL = 2 kΩ 0.00007%
Headroom THD < 0.01%, RL = 2 kΩ 20 VPP
OUTPUT
Voltage output swing low RL = 2 kΩ (V−) + 1.6 V
RL = 1 kΩ (V−) + 3.5
Voltage output swing high RL = 2 kΩ (V+) – 1.6 V
RL = 1 kΩ (V+) − 3.5
Short-circuit current, ISC Sourcing 50 85 mA
Sinking −60 –85
Closed-loop output impedance G = +1, f = 100 kHz 0.22 Ω
POWER DOWN
Enable voltage threshold (V−) + 1.45 V
Disable voltage threshold (V−) + 1.4 V
Shutdown current(1) VS = ±5 V, VENABLE = −5 V 0.85 mA
VENABLE = −15 V 1.7
Turn-on delay Time for IQ to reach 50% 2 μs
Turn-off delay Time for IQ to reach 50% 2 μs
POWER SUPPLY
Quiescent current, IQ 13 17.1 mA
(1) Amplifier has internal 250-kΩ pullup resistor to V+ pin. This pullup resistor enables the amplifier with no connection to shutdown pin.