ZHCSI49C September   2014  – March 2021

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current (Into VCC) Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Thermal Resistance Characteristics
    7. 8.7 Timing and Switching Characteristics
      1. 8.7.1  Reset Timing
        1. 8.7.1.1 Reset Timing
      2. 8.7.2  Clock Specifications
        1. 8.7.2.1 DCO in External Resistor Mode
        2. 8.7.2.2 DCO in Internal Resistor Mode
        3. 8.7.2.3 DCO Overall Tolerance Table
        4. 8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions
      3. 8.7.3  Wake-up Characteristics
        1. 8.7.3.1 Wake-up Times From Low Power Modes
      4. 8.7.4  I/O Ports
        1. 8.7.4.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.7.4.2 Inputs – Ports P1 and P2
        3. 8.7.4.3 Leakage Current – General-Purpose I/O
        4. 8.7.4.4 Outputs – General-Purpose I/O
        5. 8.7.4.5 Output Frequency – General-Purpose I/O
        6. 8.7.4.6 Typical Characteristics – Outputs
      5. 8.7.5  Power Management Module
        1. 8.7.5.1 PMM, High-Side Brownout Reset (BORH)
        2. 8.7.5.2 PMM, Low-Side SVS (SVSL)
        3. 8.7.5.3 PMM, Core Voltage
        4. 8.7.5.4 PMM, Voltage Monitor (VMON)
      6. 8.7.6  Reference Module
        1. 8.7.6.1 Voltage Reference (REF)
        2. 8.7.6.2 Temperature Sensor
      7. 8.7.7  SD24
        1. 8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
        2. 8.7.7.2 SD24 Internal Voltage Reference
        3. 8.7.7.3 SD24 External Voltage Reference
        4. 8.7.7.4 SD24 Input Range
        5. 8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
        6. 8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
        7. 8.7.7.7 Typical Characteristics
      8. 8.7.8  eUSCI
        1. 8.7.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics
        3. 8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.7.8.4 eUSCI (SPI Master Mode) Timing
        5. 8.7.8.5 eUSCI (SPI Slave Mode) Timing
        6. 8.7.8.6 eUSCI (I2C Mode) Timing
      9. 8.7.9  Timer_A
        1. 8.7.9.1 Timer_A
      10. 8.7.10 Flash
        1. 8.7.10.1 Flash Memory
      11. 8.7.11 Emulation and Debug
        1. 8.7.11.1 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagrams
    3. 9.3  CPU
    4. 9.4  Instruction Set
    5. 9.5  Operating Modes
    6. 9.6  Interrupt Vector Addresses
    7. 9.7  Special Function Registers
    8. 9.8  Flash Memory
    9. 9.9  JTAG Operation
      1. 9.9.1 JTAG Standard Interface
      2. 9.9.2 Spy-Bi-Wire Interface
      3. 9.9.3 JTAG Disable Register
    10. 9.10 Peripherals
      1. 9.10.1 Clock System
      2. 9.10.2 Power-Management Module (PMM)
      3. 9.10.3 Digital I/O
      4. 9.10.4 Watchdog Timer (WDT)
      5. 9.10.5 Timer TA0
      6. 9.10.6 Timer TA1
      7. 9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
      8. 9.10.8 Hardware Multiplier
      9. 9.10.9 SD24
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
      3. 9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
      4. 9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptor
    13. 9.13 Memory
      1. 9.13.1 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Device Identification
      2. 9.14.2 JTAG Identification
  10. 10Applications, Implementation, and Layout
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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说明

德州仪器 (TI) MSP430i204x、MSP430I203x 和 MSP430I202x 微控制器 (MCU) 属于 MSP430 计量和监控产品系列。该架构和集成外设与五种低功耗模式相结合并经过优化,可在便携式和电池供电测量应用中延长电池寿命。该器件具有功能强大的 16 位 RISC CPU、16 位寄存器和常数发生器,有助于实现最大编码效率。数控振荡器 (DCO) 可以让器件在不到 5µs 的时间内从低功耗模式唤醒至激活模式。

MSP430i204x MCU 包括四个高性能 24 位 Σ-Δ ADC,两个 eUSCI(一个 eUSCI_A 模块和一个 eUSCI_B 模块),两个 16 位计时器,一个硬件乘法器和多达 16 个 I/O 引脚。

MSP430I203x MCU 包括三个高性能 24 位 Σ-Δ ADC,两个 eUSCI(一个 eUSCI_A 模块和一个 eUSCI_B 模块),两个 16 位计时器,一个硬件乘法器和多达 16 个 I/O 引脚。

MSP430I202x MCU 包括两个高性能 24 位 Σ-Δ ADC,两个 eUSCI(一个 eUSCI_A 模块和一个 eUSCI_B 模块),两个 16 位计时器,一个硬件乘法器和多达 16 个 I/O 引脚。

这些器件的典型应用包括:电能测量、模拟和数字传感器系统、LED 照明、数字电源、电机控制、远程控制、温度调节装置、数字计时器和手持式仪表。

MSP430i204x、MSP430I203x 和 MSP430I202x MCU 由广泛的硬件和软件生态系统提供支持,随附参考设计和代码示例,便于您快速开始设计。https://www.ti.com/tool/EVM430-I2040Shttps://www.ti.com/tool/MSP-TS430RHB32A开发套件包括用于计量的 EVM430-I2040S 评估模块 (EVM) 和 MSP-TS430RHB32A 100 引脚目标开发板。https://www.ti.com/tool/MSP-EM-DESIGN-CENTER提供适用于 MSP430 MCU 的电能测量设计中心作为快速开发工具,可测量这些器件的电能。http://dev.ti.com/tirex/#/TI 还提供免费的 MSP430Ware 软件,该软件以 Code Composer Studio IDE 桌面和云版本组件的形式提供(位于 TI Resource Explorer 中)。TI E2E 支持论坛还为 MSP430 MCU 提供广泛的在线配套资料、培训和在线支持。

https://www.ti.com/lit/pdf/SLAU335如需完整的模块说明,请参阅《MSP430i2xx 系列用户指南》。

器件信息
器件型号 封装 封装尺寸
MSP430i2041TPW TSSOP (28) 9.7mm x 4.4mm
MSP430i2041TRHB VQFN (32) 5mm x 5mm