ZHCSER2D May   2013  – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 8.9  Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
    10. 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    11. 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 8.22 Crystal Oscillator, XT2
    23. 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 8.25 DCO Frequency
    26. 8.26 PMM, Brownout Reset (BOR)
    27. 8.27 PMM, Core Voltage
    28. 8.28 PMM, SVS High Side
    29. 8.29 PMM, SVM High Side
    30. 8.30 PMM, SVS Low Side
    31. 8.31 PMM, SVM Low Side
    32. 8.32 Wake-up Times From Low-Power Modes and Reset
    33. 8.33 Timer_A
    34. 8.34 Timer_B
    35. 8.35 USCI (UART Mode) Clock Frequency
    36. 8.36 USCI (UART Mode)
    37. 8.37 USCI (SPI Master Mode) Clock Frequency
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 8.42 10-Bit ADC, Timing Parameters
    43. 8.43 10-Bit ADC, Linearity Parameters
    44. 8.44 REF, External Reference
    45. 8.45 REF, Built-In Reference
    46. 8.46 Comparator_B
    47. 8.47 Flash Memory
    48. 8.48 JTAG and Spy-Bi-Wire Interface
    49. 8.49 DVIO BSL Entry
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 Bootloader – I2C
      2. 9.5.2 Bootloader – UART
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC10_A
      17. 9.9.17 CRC16
      18. 9.9.18 Reference (REF) Module Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM) (S Version)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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9.9.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see Table 9-8).

Table 9-8 Port Mapping Mnemonics and Functions
VALUEPxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION
0PM_NONENoneDVSS
1PM_CBOUT0–COMP_B output
PM_TB0CLKTB0 clock input–
2PM_ADC10CLK–ADC10CLK
PM_DMAE0DMAE0 input–
3PM_SVMOUT–SVM output
PM_TB0OUTHTB0 high-impedance input TB0OUTH–
4PM_TB0CCR0ATB0 CCR0 capture input CCI0ATB0 CCR0 compare output Out0
5PM_TB0CCR1ATB0 CCR1 capture input CCI1ATB0 CCR1 compare output Out1
6PM_TB0CCR2ATB0 CCR2 capture input CCI2ATB0 CCR2 compare output Out2
7PM_TB0CCR3ATB0 CCR3 capture input CCI3ATB0 CCR3 compare output Out3
8PM_TB0CCR4ATB0 CCR4 capture input CCI4ATB0 CCR4 compare output Out4
9PM_TB0CCR5ATB0 CCR5 capture input CCI5ATB0 CCR5 compare output Out5
10PM_TB0CCR6ATB0 CCR6 capture input CCI6ATB0 CCR6 compare output Out6
11PM_UCA1RXDUSCI_A1 UART RXD (direction controlled by USCI – input)
PM_UCA1SOMIUSCI_A1 SPI slave out master in (direction controlled by USCI)
12PM_UCA1TXDUSCI_A1 UART TXD (direction controlled by USCI – output)
PM_UCA1SIMOUSCI_A1 SPI slave in master out (direction controlled by USCI)
13PM_UCA1CLKUSCI_A1 clock input/output (direction controlled by USCI)
PM_UCB1STEUSCI_B1 SPI slave transmit enable (direction controlled by USCI)
14PM_UCB1SOMIUSCI_B1 SPI slave out master in (direction controlled by USCI)
PM_UCB1SCLUSCI_B1 I2C clock (open drain and direction controlled by USCI)
15PM_UCB1SIMOUSCI_B1 SPI slave in master out (direction controlled by USCI)
PM_UCB1SDAUSCI_B1 I2C data (open drain and direction controlled by USCI)
16PM_UCB1CLKUSCI_B1 clock input/output (direction controlled by USCI)
PM_UCA1STEUSCI_A1 SPI slave transmit enable (direction controlled by USCI)
17PM_CBOUT1NoneCOMP_B output
18PM_MCLKNoneMCLK
19PM_RTCCLKNoneRTCCLK output
20PM_UCA0RXDUSCI_A0 UART RXD (direction controlled by USCI – input)
PM_UCA0SOMIUSCI_A0 SPI slave out master in (direction controlled by USCI)
21PM_UCA0TXDUSCI_A0 UART TXD (direction controlled by USCI – output)
PM_UCA0SIMOUSCI_A0 SPI slave in master out (direction controlled by USCI)
22PM_UCA0CLKUSCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STEUSCI_B0 SPI slave transmit enable (direction controlled by USCI)
23PM_UCB0SOMIUSCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCLUSCI_B0 I2C clock (open drain and direction controlled by USCI)
24PM_UCB0SIMOUSCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDAUSCI_B0 I2C data (open drain and direction controlled by USCI)
25PM_UCB0CLKUSCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STEUSCI_A0 SPI slave transmit enable (direction controlled by USCI)
26PM_UCA3RXDUSCI_A3 UART RXD (direction controlled by USCI – input)
PM_UCA3SOMIUSCI_A3 SPI slave out master in (direction controlled by USCI)
27PM_UCA3TXDUSCI_A3 UART TXD (direction controlled by USCI – output)
PM_UCA3SIMOUSCI_A3 SPI slave in master out (direction controlled by USCI)
28PM_UCB3SIMOUSCI_B3 SPI slave in master out (direction controlled by USCI)
PM_UCB3SDAUSCI_B3 I2C data (open drain and direction controlled by USCI)
29PM_UCB3SOMIUSCI_B3 SPI slave out master in (direction controlled by USCI)
PM_UCB3SCLUSCI_B3 I2C clock (open drain and direction controlled by USCI)
30ReservedReserved
31 (0FFh)(1)PM_ANALOGDisables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals
(1) The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 9-9 lists the default settings for all pins that support port mapping.

Table 9-9 Default Mapping
PINPxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION
P4.0/P4MAP0PM_UCB1STE/PM_UCA1CLKUSCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1PM_UCB1SIMO/PM_UCB1SDAUSCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.2/P4MAP2PM_UCB1SOMI/PM_UCB1SCLUSCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3PM_UCB1CLK/PM_UCA1STEUSCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4PM_UCA1TXD/PM_UCA1SIMOUSCI_A1 UART TXD (Direction controlled by USCI – output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5PM_UCA1RXD/PM_UCA1SOMIUSCI_A1 UART RXD (Direction controlled by USCI – input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6PM_UCA3TXD/PM_UCA3SIMOUSCI_A3 UART TXD (Direction controlled by USCI – output)
USCI_A3 SPI slave in master out (direction controlled by USCI)
P4.7/P4MAP7PM_UCA3RXD/PM_UCA3SOMIUSCI_A3 UART RXD (Direction controlled by USCI – input)
USCI_A3 SPI slave out master in (direction controlled by USCI)