ZHCSO29 July   2021 LP5890

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short and Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 Soft_Reset Command
        4. 8.5.3.4 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC10
      7. 8.7.7  FC11
      8. 8.7.8  FC12
      9. 8.7.9  FC13
      10. 8.7.10 FC14
      11. 8.7.11 FC15
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open and Short Read
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

FC4

FC4 is shown in FC4 Register and described in FC4 Register Field Descriptions.

Figure 8-29 FC4 Register
47464544434241403938373635343332
RESERVEDDE_COUPLE3_EN DE_COUPLE3DE_COUPLE2FIRST_LINE_DIMLG_CAURSE_BLG_CAURSE_GLG_CAURSE_R
R-000bR/W-0bR/W-1000bR/W-0bR/W-0000bR/W-0bR/W-0bR/W-0b
31302928272625242322212019181716
RESERVEDSR_ON_BSR_ON_GSR_ON_RSR_OFF_BSR_OFF_GSR_OFF_RLG_FINE_BLG_FINE_GLG_FINE_R
R-0000bR/W-01bR/W-01bR/W-01bR/W-0bR/W-0bR/W-0bR-000b
1514131211109876543210
RESERVEDSCAN_REVRESERVEDIMAXRESERVED
R-0bR/W-1bR-00 0000 0000bR/W-0bR-000b
Table 8-11 FC4 Register Field Descriptions
BitFieldTypeResetDescription
2-0RESERVEDR000b
3IMAXR/W0bSet the maximum current of each channel
0b: 10mA maximum
01b: 20 mA maximum
13-4RESERVEDR0000000000b
14SCAN_REVR/W1bWhen 2 device stackable or 3 devices stackable, the scan lines PCB layout is reversed. For the proper scan and SRAM read sequence, SCAN_REV register is provided.
0b: the PCB layout sequence is L0-L15, L16-L31.
1b: the PCB layout sequence is L0-L15, L31-L16.
15RESERVEDR0b
16LG_FINE_RR/W0bEnable the Red brightness compensation level fine range
0b: disable
1b: enable
17LG_FINE_GR/W0bEnable the Green brightness compensation level fine range
0b: disable
1b: enable
18LG_FINE_BR/W0bEnable the Blue brightness compensation level fine range
0b: disable
1b: enable
19SR_OFF_RR/W0bSlew rate control function when Red turns off operation
0b: slow slew rate.
1b: fast slew rate.
20SR_OFF_GR/W0bSlew rate control function when Green turns off operation
0b: slow slew rate.
1b: fast slew rate.
21SR_OFF_BR/W0bSlew rate control function when Blue turns off operation
0b: slow slew rate.
1b: fast slew rate.
23-22SR_ON_RR/W01bSlew rate control function when Red turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
25-24SR_ON_GR/W01bSlew rate control function when Green turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
27-26SR_ON_BR/W01bSlew rate control function when Blue turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
31-28RESERVEDR0000b
32LG_CAURSE_RR/W0bEnable the Red brightness compensation level caurse range
0b: disable
1b: enable
33LG_CAURSE_GR/W0bEnable the Green brightness compensation level caurse range
0b: disable
1b: enable
34LG_CAURSE_BR/W0bEnable the Blue brightness compensation level caurse range
0b: disable
1b: enable
38-35FIRST_LINE_DIMR/W0000bAdjust the first line dim level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
39DE_COUPLE2R/W0bDecoupling between ON and OFF channels
0b: disabled
1b: enabled
43-40DE_COUPLE3R/W1000bSet decoupling enhancement level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
44DE_COUPLE3_ENR/W0bEnable decoupling enhancement
0b: disabled
1b: enabled
47-45RESERVEDR000b