ZHCSDH0C December   2014  – January 2018 LP3907-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 器件比较 台式机
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset (POR) Threshold/Function
    10. 7.10 I2C Interface Timing Requirements
    11. 7.11 Typical Characteristics — LDO
    12. 7.12 Typical Characteristics — Bucks
    13. 7.13 Typical Characteristics — Buck1
    14. 7.14 Typical Characteristics — Buck2
    15. 7.15 Typical Characteristics — Bucks
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Linear Low Dropout Regulators (LDOs)
        2. 8.3.1.2 No-Load Stability
        3. 8.3.1.3 LDO and LDO2 Control Registers
      2. 8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.2.1  Functional Description
        2. 8.3.2.2  Circuit Operation Description
        3. 8.3.2.3  PWM Operation
        4. 8.3.2.4  Internal Synchronous Rectification
        5. 8.3.2.5  Current Limiting
        6. 8.3.2.6  PFM Operation
        7. 8.3.2.7  SW1, SW2 Operation
        8. 8.3.2.8  SW1, SW2 Control Registers
        9. 8.3.2.9  Soft Start
        10. 8.3.2.10 Low Dropout Operation
        11. 8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.2.12 Power-Up Sequencing Using the EN_T Function
      3. 8.3.3 Flexible Power-On Reset (Power Good with Delay)
      4. 8.3.4 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
      2. 8.5.2 Factory Programmable Options
    6. 8.6 Register Maps
      1. 8.6.1 LP3907-Q1 Control Registers
        1. 8.6.1.1  Interrupt Status Register (ISRA) 0x02
        2. 8.6.1.2  Control 1 Register (SCR1) 0x07
        3. 8.6.1.3  EN_DLY Preset Delay Sequence After EN_T Assertion
        4. 8.6.1.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10
        5. 8.6.1.5  Buck and LDO Status Register (BKLDOSR) – 0x11
        6. 8.6.1.6  Buck Voltage Change Control Register 1 (VCCR) – 0x20
        7. 8.6.1.7  Buck1 Target Voltage 1 Register (B1TV1) – 0x23
        8. 8.6.1.8  Buck1 Target Voltage 2 Register (B1TV2) – 0x24
        9. 8.6.1.9  Buck1 Ramp Control Register (B1RC) - 0x25
        10. 8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29
        11. 8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A
        12. 8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B
        13. 8.6.1.13 Buck Function Register (BFCR) – 0x38
        14. 8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39
        15. 8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
          1. 9.2.2.1.1 Inductors for SW1 And SW2
            1. 9.2.2.1.1.1 Method 1:
            2. 9.2.2.1.1.2 Method 2:
          2. 9.2.2.1.2 External Capacitors
        2. 9.2.2.2 LDO Capacitor Selection
          1. 9.2.2.2.1 Input Capacitor
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Capacitor Characteristics
          4. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.2.6 I2C Pullup Resistor
        3. 9.2.2.3 Operation Without I2C Interface
          1. 9.2.2.3.1 High VIN High-Load Operation
          2. 9.2.2.3.2 Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 DSBGA Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations of WQFN Package
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 商标
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 说明

LP3907-Q1 器件是专为低功耗 FPGA、微处理器和 DSP 优化的多功能、可编程电源管理单元 (PMU)。该器件集成了两个具有动态电压调节 (DVS) 功能的高效 1A、600mA 降压直流/直流转换器、两个 300mA 线性稳压器和一个 400kHz I2C 接口，使主机控制器可以访问该器件的内部控制寄存器。LP3907-Q1 还 具有 可编程的加电序列。该器件是一款经过 AECQ-100 1 级认证的汽车级产品。

具备诸多功能， 其中包括可编程的加电序列、通信控制 (I2C)、动态电压调节、过流保护、电源正常指示、同步整流、热关断以及欠压锁定。对于 需要 轻负载的应用，此款高效同步开关降压稳压器可进入 PFM 模式，以较低的开关频率和电源电流运行，从而在极轻负载下保持高效率。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LP3907-Q1 WQFN (24) 4.00mm x 4.00mm
DSBGA (25) 2.49mm × 2.49mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。