The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but use good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature. Using Y5V-rated capacitors is discouraged because of large variations in capacitance.

Maximum supported ESR range across complete temperature (−40°C to +125°C) and load current range (0mA−150mA) is less than 1Ω. For existing implementations, where different capacitor types with higher ESR values are used, use a low ESR, 100nF MLCC capacitor. Place this capacitor as close as possible to the device output (V_OUT) pin.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value.