ZHCSU12M March   2000  – June 2025 LP2982

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors (Legacy Chip)
        2. 7.1.1.2 Recommended Capacitors (New Chip)
      2. 7.1.2 Input Capacitor Requirements
      3. 7.1.3 Output Capacitor Requirements
      4. 7.1.4 Noise Bypass Capacitor (CBYPASS)
      5. 7.1.5 Reverse Current
      6. 7.1.6 Power Dissipation (PD)
      7. 7.1.7 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/ OFF Input Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 器件和文档支持
    1. 8.1 器件命名规则
    2. 8.2 第三方产品免责声明
    3. 8.3 文档支持
      1. 8.3.1 相关文档
    4. 8.4 接收文档更新通知
    5. 8.5 支持资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.4 Thermal Information

THERMAL METRIC (1) Legacy Chip (2) New Chip (2) UNIT
DBV (SOT23-5) DBV (SOT23-5)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 121.8 77.9 °C/W
RθJB Junction-to-board thermal resistance 29.5 47.2 °C/W
ψJT Junction-to-top characterization parameter 16.1 15.9 °C/W
ψJB Junction-to-board characterization parameter 29.0 46.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report.