SNAS517E November   2011  – September 2015 LMP91050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain Amplifier
      2. 8.3.2 External Filter
      3. 8.3.3 Offset Adjust
      4. 8.3.4 Common-Mode Generation
      5. 8.3.5 CSB
        1. 8.3.5.1 SCLK
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1 Interface Pins
        2. 8.5.1.2 Communication Protocol
        3. 8.5.1.3 Registers Organization
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration
      2. 8.6.2 DAC Configuration
      3. 8.6.3 SDIO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

Figure 33 shows a layout example for the LMP91050. All components should be placed as close as possible to the device, especially the bypass capacitors to VDD (CBypass1 and CBypass2).

11.2 Layout Example

LMP91050 layout_SNAS517.gif Figure 33. LMP91050 Layout Example