SNAS517E November   2011  – September 2015 LMP91050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain Amplifier
      2. 8.3.2 External Filter
      3. 8.3.3 Offset Adjust
      4. 8.3.4 Common-Mode Generation
      5. 8.3.5 CSB
        1. 8.3.5.1 SCLK
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1 Interface Pins
        2. 8.5.1.2 Communication Protocol
        3. 8.5.1.3 Registers Organization
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration
      2. 8.6.2 DAC Configuration
      3. 8.6.3 SDIO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 26 shows a typical NDIR sensing circuit with a bandpass filter with a high frequency cutoff of approximately 100 Hz. The lowpass filter at the output has a cutoff of approximately 110 Hz.

9.2 Typical Application

LMP91050 30164111.gif Figure 26. Typical NDIR Sensing Application Circuit

9.2.1 Design Requirements

The design requirements for using the LMP91050 in an application basically include the following:

  • Determine the characteristics of the thermopile and the appropriate gain and common mode voltage that will maximize the dynamic range of the sensor. Consult the manufacturer’s data sheet.
  • Selecting an analog-to-digital converter that supports the needed resolution and update rate.
  • Determining the bandwidth of the inter-stage low-pass filter to limit the noise imposed on the signal
  • An SPI interface to a microcontroller or other logic device is required in order to configure the LMP91050.

9.2.2 Detailed Design Procedure

The basic design procedure is as follows:

  • Select the appropriate inter-stage bandpass filter bandwidth. Note that the common mode voltage (CMOUT) is connected to both the thermopile and the bandpass filter, as shown in Figure 26.
  • TI recommends that a lowpass filter be inserted between the OUT pin and the input to the ADC, to further reduce noise on the signal and prevent aliasing.
  • Power supply bypassing as shown in figure 32 is recommended.
  • Based on the thermopile characteristics, select the common-mode voltage and gain to be programmed into the LMP91050. CMOUT should be selected to center the expected dynamic range of the thermopile within the full scale range of the ADC to the best extent possible. The gain should be selected to maximize the signal range at the ADC input, but should allow some headroom below full scale to prevent clipping. The gain should also compensate, if possible, for any loss due to the filters in the signal path.
  • The internal DAC can be programmed to further optimize the signal range on the OUT pin. See Offset Adjust for further information.

9.2.3 Application Curves

LMP91050 30164133.gif Figure 27. PGA1 Small Signal Bandwidth
LMP91050 30164134.gif Figure 29. Power Supply Rejection Ratio vs. Frequency
LMP91050 30164139.gif Figure 31. DAC DC Sweep With VDD = 3.3 V
LMP91050 30164132.gif Figure 28. PGA2 Small Signal Bandwidth
LMP91050 30164145.gif Figure 30. Input-Referred Noise Density vs. Frequency
LMP91050 30164140.gif Figure 32. DAC DC Sweep With VDD = 5 V