In the independent mode, each DPLL can select a reference as preferred. DPLL's can share the same reference, or each select a different reference. At start-up, each APLL will lock to the XO input after initialization and operate in free-run mode. Once a valid DPLL reference input is detected, each DPLL begins lock acquisition on independent reference priority. Each DPLL's TDC compares the phase of the selected reference input clock and the FB divider clock from the respective VCO and generates a digital correction word corresponding to the phase error. The correction word is filtered by the digital loop filter (DLF), and the DLF output adjusts the APLL N divider SDM to pull the VCO frequency into lock with the reference input.

As each DPLL can work independently in this mode, the DPLLs can lock or unlock without impacting other channels.

When selecting an XO frequency, TI recommends to avoid ratios falling near integer or half integer boundaries to minimize spurious noise. Ideally, the selected frequency that would ensure each APLL fractional-N divide ratio (NUM/DEN) is between 0.125 to 0.875 with the exception of the range between 0.45 to 0.55. Higher frequency XO is better for jitter performance, especially for APLL1 and APLL2 outputs. If the XO frequency or phase noise performance has gap for APLL1 or APLL2, there is an option to adopt cascaded mode using APLL3 as the reference to APLL1 or APLL2.