SNAS703 April   2017 LMK04828-EP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Timing Diagram
    8. 7.8 Typical Characteristics - Clock Output AC Characteristics
  8. Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1  Jitter Cleaning
      2. 9.1.2  JEDEC JESD204B Support
      3. 9.1.3  Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
      4. 9.1.4  VCXO or Crystal Buffered Output
      5. 9.1.5  Frequency Holdover
      6. 9.1.6  PLL2 Integrated Loop Filter Poles
      7. 9.1.7  Internal VCOs
      8. 9.1.8  External VCO Mode
      9. 9.1.9  Clock Distribution
        1. 9.1.9.1 Device Clock Divider
        2. 9.1.9.2 SYSREF Clock Divider
        3. 9.1.9.3 Device Clock Delay
        4. 9.1.9.4 SYSREF Delay
        5. 9.1.9.5 Glitchless Half Step and Glitchless Analog Delay
        6. 9.1.9.6 Programmable Output Formats
        7. 9.1.9.7 Clock Output Synchronization
      10. 9.1.10 0-Delay
      11. 9.1.11 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How To Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
        2. 9.3.3.2 Dynamic Digital Delay
        3. 9.3.3.3 Single and Multiple Dynamic Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
      6. 9.3.6 Digital Lock Detect
        1. 9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 During Holdover
        3. 9.3.7.3 Exiting Holdover
        4. 9.3.7.4 Holdover Frequency Accuracy and DAC Performance
        5. 9.3.7.5 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Device Functional Modes
      1. 9.4.1 DUAL PLL
      2. 9.4.2 0-DELAY Dual PLL
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 SPI LOCK
        2. 9.5.1.2 SYSREF_CLR
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
    7. 9.7 Device Register Descriptions
      1. 9.7.1 System Functions
        1. 9.7.1.1 RESET, SPI_3WIRE_DIS
        2. 9.7.1.2 POWERDOWN
        3. 9.7.1.3 ID_DEVICE_TYPE
        4. 9.7.1.4 ID_PROD[15:8], ID_PROD
        5. 9.7.1.5 ID_MASKREV
        6. 9.7.1.6 ID_VNDR[15:8], ID_VNDR
      2. 9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
        1. 9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
        2. 9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
        3. 9.7.2.3 DCLKoutX_DDLYd_CNTH, DCLKoutX_DDLYd_CNTL
        4. 9.7.2.4 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
        5. 9.7.2.5 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
        6. 9.7.2.6 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
        7. 9.7.2.7 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
        8. 9.7.2.8 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
      3. 9.7.3 SYSREF, SYNC, and Device Config
        1. 9.7.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
        2. 9.7.3.2  SYSREF_CLKin0_MUX, SYSREF_MUX
        3. 9.7.3.3  SYSREF_DIV[12:8], SYSREF_DIV[7:0]
        4. 9.7.3.4  SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
        5. 9.7.3.5  SYSREF_PULSE_CNT
        6. 9.7.3.6  PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
        7. 9.7.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
        8. 9.7.3.8  DDLYd_SYSREF_EN, DDLYdX_EN
        9. 9.7.3.9  DDLYd_STEP_CNT
        10. 9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
        11. 9.7.3.11 SYNC_DISSYSREF, SYNC_DISX
        12. 9.7.3.12 Fixed Register
      4. 9.7.4 (0x146 - 0x149) CLKin Control
        1. 9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
        2. 9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
        3. 9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
        4. 9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
      5. 9.7.5 RESET_MUX, RESET_TYPE
      6. 9.7.6 (0x14B - 0x152) Holdover
        1. 9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
        2. 9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
        3. 9.7.6.3 DAC_TRIP_LOW
        4. 9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
        5. 9.7.6.5 DAC_CLK_CNTR
        6. 9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
        7. 9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
      7. 9.7.7 (0x153 - 0x15F) PLL1 Configuration
        1. 9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
        2. 9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
        3. 9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
        4. 9.7.7.4 PLL1_N
        5. 9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
        6. 9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
        7. 9.7.7.7 PLL1_R_DLY, PLL1_N_DLY
        8. 9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
      8. 9.7.8 (0x160 - 0x16E) PLL2 Configuration
        1. 9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
        2. 9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
        3. 9.7.8.3 PLL2_N_CAL
        4. 9.7.8.4 PLL2_FCAL_DIS, PLL2_N
        5. 9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
        6. 9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
        7. 9.7.8.7 PLL2_LF_R4, PLL2_LF_R3
        8. 9.7.8.8 PLL2_LF_C4, PLL2_LF_C3
        9. 9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
      9. 9.7.9 (0x16F - 0x1FFF) Misc Registers
        1. 9.7.9.1  Fixed Register 0x171
        2. 9.7.9.2  Fixed Register 0x172
        3. 9.7.9.3  PLL2_PRE_PD, PLL2_PD
        4. 9.7.9.4  OPT_REG_1
        5. 9.7.9.5  OPT_REG_2
        6. 9.7.9.6  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
        7. 9.7.9.7  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
        8. 9.7.9.8  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
        9. 9.7.9.9  RB_DAC_VALUE
        10. 9.7.9.10 RB_HOLDOVER
        11. 9.7.9.11 SPI_LOCK
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
      2. 10.1.2 Driving CLKin and OSCin Inputs
        1. 10.1.2.1 Driving CLKin Pins With a Differential Source
        2. 10.1.2.2 Driving CLKin or OSCin Pins With a Single-Ended Source
      3. 10.1.3 Using AC-Coupled Clock Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Clock Architect
          2. 10.2.2.1.2 Clock Design Tool
        2. 10.2.2.2 Device Configuration and Simulation
        3. 10.2.2.3 Device Programming
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Clock Architect
        2. 13.1.1.2 Clock Design Tool
        3. 13.1.1.3 TICS Pro
      2. 13.6   Electrostatic Discharge Caution
      3. 13.7   Glossary
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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订购信息

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (2)
MIN MAX UNIT
VCC Supply voltage (1) –0.3 3.6 V
VIN Input voltage –0.3 (VCC + 0.3) V
TL Lead temperature (solder 4 seconds) 260 °C
TJ Junction temperature 150 °C
IIN Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) ±5 mA
MSL Moisture sensitivity level 3
Tstg Storage temperature –65 150 °C
Never to exceed 3.6 V.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
Machine Model (MM) ±150
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TJ Junction temperature 125 °C
TA Ambient temperature –55 25 105 °C
VCC Supply voltage 3.15 3.3 3.45 V

Thermal Information

THERMAL METRIC(1) LMK04828-EP UNIT
NKD (WQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance(2) 24.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 6.1 °C/W
RθJB Junction-to-board thermal resistance(4) 3.5 °C/W
ψJT Junction-to-top characterization parameter(5) 0.1 °C/W
ψJB Junction-to-board characterization parameter(6) 3.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 0.7 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Electrical Characteristics

(3.15 V < VCC < 3.45 V, –55 °C < TA < +105°C. Typical values at VCC = 3.3 V, TA = 25 °C, at the recommended operating conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC_PD Power-down supply current 1 3 mA
ICC_CLKS Supply current(2) 14 HSDS 8 mA clocks enabled
PLL1 and PLL2 locked.
565 670 mA
CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKin Clock input frequency 0.001 750 MHz
SLEWCLKin Clock input slew rate (3) 20% to 80% 0.15 0.5 V/ns
VIDCLKin Differential clock input voltage(1)
See Figure 4
AC-coupled 0.125 1.55 |V|
VSSCLKin 0.25 3.1 Vpp
VCLKin Clock input
Single-ended input voltage
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 0 (Bipolar)
0.25 2.4 Vpp
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 1 (MOS)
0.35 2.4 Vpp
|VCLKinX-offset| DC offset voltage between
CLKinX/CLKinX* (CLKinX* - CLKinX)
Each pin is AC-coupled, CLKin0/1/2
CLKinX_TYPE = 0 (Bipolar)
0 |mV|
Each pin is AC-coupled, CLKin0/1
CLKinX_TYPE = 1 (MOS)
55 |mV|
DC offset voltage between
CLKin2/CLKin2* (CLKin2* - CLKin2)
Each pin is AC-coupled
CLKinX_TYPE = 1 (MOS)
20 |mV|
VCLKin- VIH High input voltage DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 1 (MOS)
2 VCC V
VCLKin– VIL Low input voltage 0 0.4 V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
fFBCLKin Clock input frequency for
0-delay with external feedback.
AC-coupled
CLKinX_TYPE = 0 (Bipolar)
0.001 750 MHz
fFin Clock input frequency for
external VCO mode
AC-coupled (4)
CLKinX_TYPE = 0 (Bipolar)
0.001 3100 MHz
Clock input frequency for
distribution mode
AC-coupled
CLKinX_TYPE = 0 (Bipolar)
0.001 3200
VFBCLKin/Fin Single-ended clock input voltage AC-coupled
CLKinX_TYPE = 0 (Bipolar)
0.25 2 Vpp
SLEWFBCLKin/Fin Slew rate on CLKin (3) AC-coupled; 20% to 80%;
(CLKinX_TYPE = 0)
0.15 0.5 V/ns
PLL1 SPECIFICATIONS
fPD1 PLL1 phase detector frequency 40 MHz
ICPout1SOURCE PLL1 charge pump source current (5) VCPout1 = VCC/2, PLL1_CP_GAIN = 0 50 µA
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 150
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 250
VCPout1 = VCC/2, PLL1_CP_GAIN = 14 1450
VCPout1 = VCC/2, PLL1_CP_GAIN = 15 1550
ICPout1SINK PLL1 Charge pump sink current (5) VCPout1=VCC/2, PLL1_CP_GAIN = 0 –50 µA
VCPout1=VCC/2, PLL1_CP_GAIN = 1 –150
VCPout1=VCC/2, PLL1_CP_GAIN = 2 –250
VCPout1=VCC/2, PLL1_CP_GAIN = 14 –1450
VCPout1=VCC/2, PLL1_CP_GAIN = 15 –1550
ICPout1%MIS Charge pump sink / source mismatch VCPout1 = VCC/2, T = 25 °C 1% 10%
ICPout1VTUNE Magnitude of charge pump current variation vs. charge pump voltage 0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C
4%
ICPout1%TEMP Charge pump current vs. temperature variation 4%
ICPout1TRI Charge pump TRI-STATE leakage current 0.5 V < VCPout < VCC - 0.5 V 10 nA
PN10kHz PLL 1/f Noise at 10-kHz offset. Normalized to 1-GHz Output Frequency PLL1_CP_GAIN = 350 µA –117 dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
PN1Hz Normalized phase noise contribution PLL1_CP_GAIN = 350 µA –221.5 dBc/Hz
PLL1_CP_GAIN = 1550 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin PLL2 reference input (7) 500 MHz
SLEWOSCin PLL2 reference clock minimum slew rate on OSCin (3) 20% to 80% 0.15 0.5 V/ns
VOSCin Input voltage for OSCin or OSCin* AC-coupled; Single-ended
(Unused pin AC-coupled to GND)
0.2 2.4 Vpp
VIDOSCin Differential voltage swing
See Figure 4
AC-coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
|VOSCin-offset| DC offset voltage between
OSCin/OSCin* (OSCinX* - OSCinX)
Each pin is AC-coupled 20 |mV|
fdoubler_max Doubler input frequency (6) EN_PLL2_REF_2X = 1(8);
OSCin Duty Cycle 40% to 60%
155 MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
FXTAL Crystal frequency range Fundamental mode crystal
ESR = 200 Ω (10 to 30 MHz)
ESR = 125 Ω (30 to 40 MHz)
10 40 MHz
CIN Input capacitance of OSCin port –40 to 85 °C 1 pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
fPD2 Phase detector frequency (6) 155 MHz
ICPoutSOURCE PLL2 charge pump source current (5) VCPout2 = VCC/2, PLL2_CP_GAIN = 0 100 µA
VCPout2 = VCC/2, PLL2_CP_GAIN = 1 400
VCPout2 = VCC/2, PLL2_CP_GAIN = 2 1600
VCPout2 = VCC/2, PLL2_CP_GAIN = 3 3200
ICPoutSINK PLL2 charge pump sink current (5) VCPout2 = VCC/2, PLL2_CP_GAIN = 0 –100 µA
VCPout2 = VCC/2, PLL2_CP_GAIN = 1 –400
VCPout2 = VCC/2, PLL2_CP_GAIN = 2 –1600
VCPout2 = VCC/2, PLL2_CP_GAIN = 3 –3200
ICPout2%MIS Charge pump sink/source mismatch VCPout2 = VCC/2, TA = 25°C 1% 10%
ICPout2VTUNE Magnitude of charge pump current vs. charge pump voltage variation 0.5 V < VCPout2 < VCC – 0.5 V 4%
ICPout2%TEMP Charge pump current vs. temperature variation 4%
ICPout2TRI Charge pump leakage 0.5 V < VCPout2 < VCC – 0.5 V 20 nA
PN10kHz PLL 1/f noise at 10-kHz offset(9). Normalized to
1-GHz output frequency
PLL2_CP_GAIN = 400 µA –118 dBc/Hz
PLL2_CP_GAIN = 3200 µA –121
PN1Hz Normalized phase noise contribution(10) PLL2_CP_GAIN = 400 µA –222.5 dBc/Hz
PLL2_CP_GAIN = 3200 µA –227
INTERNAL VCO SPECIFICATIONS
fVCO LMK04828-EP VCO tuning range VCO0 2450 2755 MHz
VCO1 2875 3080
KVCO LMK04828-EP fine tuning sensitivity VCO0 Lower end 17 MHz/V
Higher end 27
VCO1 Lower end 17
Higher end 23
|ΔTCL| Allowable temperature drift for continuous lock(11) After programming for lock, no changes to output configuration are permitted to assure continuous lock. 160 °C
NOISE FLOOR
L(f)CLKout LMK04828-EP, VCO0, noise floor
20-MHz offset (18)
245.76 MHz LVDS –156.3 dBc/Hz
HSDS 6 mA –158.4
HSDS 8 mA –159.3
HSDS 10 mA –158.9
LVPECL16 with 240 Ω –161.6
LVPECL20 with 240 Ω –162.5
LCPECL –162.1
L(f)CLKout LMK04828-EP, VCO1, noise floor
20-MHz offset (18)
245.76 MHz LVDS –155.7 dBc/Hz
HSDS 6 mA –157.5
HSDS 8 mA –158.1
HSDS 10 mA –157.7
LVPECL16 with 240 Ω –160.3
LVPECL20 with 240 Ω –161.1
LCPECL –160.8
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO(12)
L(f)CLKout LMK04828-EP
VCO0
SSB phase noise (18)
245.76 MHz
Offset = 1 kHz –124.3 dBc/Hz
Offset = 10 kHz –134.7
Offset = 100 kHz –136.5
Offset = 1 MHz –148.4
Offset = 10 MHz LVDS –156.4
HSDS 8 mA –159.1
LVPECL16 with 240 Ω –160.8
L(f)CLKout LMK04828-EP
VCO1
SSB phase noise (18)
245.76 MHz
Offset = 1 kHz –124.2 dBc/Hz
Offset = 10 kHz –134.4
Offset = 100 kHz –135.2
Offset = 1 MHz –151.5
Offset = 10 MHz LVDS –159.9
HSDS 8 mA –155.8
LVPECL16 with 240 Ω –158.1
CLKout CLOSED LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO(12)
JCLKout LMK04828-EP, VCO0
fCLKout = 245.76 MHz
Integrated RMS jitter (18)
LVDS, BW = 100 Hz to 20 MHz 112 fs rms
LVDS, BW = 12 kHz to 20 MHz 109
HSDS 8 mA, BW = 100 Hz to 20 MHz 102
HSDS 8 mA, BW = 12 kHz to 20 MHz 99
LVPECL16 with 240 Ω,
BW = 100 Hz to 20 MHz
98
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz
95
LCPECL with 240 Ω,
BW = 100 Hz to 20 MHz
96
LCPECL with 240 Ω,
BW = 12 kHz to 20 MHz
93
LMK04828-EP, VCO1
fCLKout = 245.76 MHz
Integrated RMS jitter (18)
LVDS, BW = 100 Hz to 20 MHz 108 fs rms
LVDS, BW = 12 kHz to 20 MHz 105
HSDS 8 mA, BW = 100 Hz to 20 MHz 98
HSDS 8 mA, BW = 12 kHz to 20 MHz 94
LVPECL16 with 240 Ω,
BW = 100 Hz to 20 MHz
93
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz
90
LCPECL with 240 Ω,
BW = 100 Hz to 20 MHz
91
LCPECL with 240 Ω,
BW = 12 kHz to 20 MHz
88
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
fCLKout-start-up Default output clock frequency at device power on (13) LMK04828-EP 315 MHz
fOSCout OSCout frequency See (6) 500 MHz
CLOCK SKEW AND DELAY
|TSKEW| DCLKoutX to SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC-coupled (14)
Same pair, same format(15)
SDCLKoutY_MUX = 0 (device clock)
25 |ps|
Maximum DCLKoutX or SDCLKoutY
to DCLKoutX or SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC-coupled
Any pair, same format (15)
SDCLKoutY_MUX = 0 (device clock)
50
tsJESD204B SYSREF to device clock setup time base reference.
See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required.
SDCLKoutY_MUX = 1 (SYSREF)
SYSREF_DIV = 30
SYSREF_DDLY = 8 (global)
SDCLKoutY_DDLY = 1 (2 cycles, local)
DCLKoutX_MUX = 1 (Div + DCC + HS)
DCLKoutX_DIV = 30
DCLKoutX_DDLY_CNTH = 7
DCLKoutX_DDLY_CNTL = 6
DCLKoutX_HS = 0
SDCLKoutY_HS = 0
–80 ps
tPDCLKin0_
SDCLKout1
Propagation delay from CLKin0 to SDCLKout1 CLKin0_OUT_MUX = 0 (SYSREF Mux)
SYSREF_CLKin0_MUX = 1 (CLKin0)
SDCLKout1_PD = 0
SDCLKout1_DDLY = 0 (Bypass)
SDCLKout1_MUX = 1 (SR)
EN_SYNC = 1
LVPECL16 with 240 Ω
0.65 ns
fADLYmax Maximum analog delay frequency DCLKoutX_MUX = 4 1536 MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout)
VOD Differential output voltage T = 25°C, DC measurement
AC-coupled to receiver input
RL = 100-Ω differential termination
395 |mV|
ΔVOD Change in magnitude of VOD for complementary output states –60 60 mV
VOS Output offset voltage 1.125 1.25 1.375 V
ΔVOS Change in VOS for complementary output states 35 |mV|
TR / TF Output rise time 20% to 80%, RL = 100 Ω, 245.76 MHz 180 ps
Output fall time 80% to 20%, RL = 100 Ω
ISA
ISB
Output short-circuit current - single-ended Single-ended output shorted to GND
T = 25 °C
–24 24 mA
ISAB Output short-circuit current - differential Complimentary outputs tied together –12 12 mA
6-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH T = 25 °C, DC measurement
Termination = 50 Ω to
VCC – 1.42 V
VCC – 1.05
VOL VCC – 1.64
VOD Differential output voltage 590 |mV|
ΔVOD Change in VOD for complementary output states –80 80 mVpp
8-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
TR / T F Output rise time 245.76 MHz, 20% to 80%, RL = 100 Ω 170 ps
Output fall time 245.76 MHz, 80% to 20%, RL = 100 Ω
VOH DC measurement
Termination = 50 Ω to VCC – 1.64 V
VCC – 1.26
VOL VCC – 2.06
VOD Differential output voltage 800 |mV|
ΔVOD Change in VOD for complementary output states –115 115 mVpp
10-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH T = 25 °C, DC measurement
Termination = 50 Ω to
VCC – 1.43 V
VCC – 0.99
VOL VCC – 1.97
VOD 980 mVpp
ΔVOD Change in VOD for complementary output states –115 115 mVpp
LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
TR / TF 20% to 80% output rise RL = 100 Ω, emitter resistors = 240 Ω to GND
DCLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
150 ps
80% to 20% output fall time
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH Output high voltage DC Measurement
Termination = 50 Ω to
VCC – 2 V
VCC – 1.04 V
VOL Output low voltage VCC – 1.80 V
VOD Output voltage
See Figure 5
760 |mV|
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH Output high voltage DC Measurement
Termination = 50 Ω to VCC – 2.3 V
VCC – 1.09 V
VOL Output low voltage VCC – 2.05 V
VOD Output voltage
See Figure 5
960 |mV|
LCPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH Output high voltage DC Measurement
Termination = 50 Ω to 0.5 V
1.57 V
VOL Output low voltage 0.62 V
VOD Output voltage
See Figure 5
950 |mV|
LVCMOS CLOCK OUTPUTS (OSCout)
fCLKout Maximum frequency
See (16)
5-pF Load 250 MHz
VOH Output high voltage 1-mA Load VCC – 0.1 V
VOL Output low voltage 1-mA Load 0.1 V
IOH Output high current (source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output low current (sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK Output duty cycle(17) VCC/2 to VCC/2,
FCLK = 100 MHz, T = 25°C
50%
TR Output rise time 20% to 80%, RL = 50 Ω, CL = 5 pF 400 ps
TF Output fall time 80% to 20%, RL = 50 Ω, CL = 5 pF 400 ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO)
VOH High-level output voltage IOH = –500 µA
CLKin_SELX_TYPE = 3 or 4
Status_LDX_TYPE = 3 or 4
RESET_TYPE = 3 or 4
VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA
CLKin_SELX_TYPE = 3, 4, or 6
Status_LDX_TYPE = 3, 4, or 6
RESET_TYPE = 3, 4, or 6
0.4 V
DIGITAL OUTPUT (SDIO)
VOH High-level output voltage IOH = –500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0
VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0 or 1
0.4 V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*)
VIH High-level input voltage 1.2 VCC V
VIL Low-level input voltage 0.4 V
DIGITAL INPUTS (CLKinX_SEL)
IIH High-level input current
VIH = VCC
CLKin_SELX_TYPE = 0,
(high impedance)
–5 5 µA
CLKin_SELX_TYPE = 1 (pullup) –5 5
CLKin_SELX_TYPE = 2 (pulldown) 10 80
IIL Low-level input current
VIL = 0 V
CLKin_SELX_TYPE = 0,
(high impedance)
–5 5 µA
CLKin_SELX_TYPE = 1 (pullup) –40 –5
CLKin_SELX_TYPE = 2 (pulldown) –5 5
DIGITAL INPUT (RESET/GPO)
IIH High-level input current
VIH = VCC
RESET_TYPE = 2
(pulldown)
10 80 µA
IIL Low-level input current
VIL = 0 V
RESET_TYPE = 0 (high impedance) –5 5 µA
RESET_TYPE = 1 (pullup) –40 –5
RESET_TYPE = 2 (pulldown) –5 5
DIGITAL INPUTS (SYNC)
IIH High-level input current VIH = VCC 25 µA
IIL Low-level input current VIL = 0 V –5 5
DIGITAL INPUTS (SCK, SDIO, CS*)
IIH High-level input current VIH = VCC –5 5 µA
IIL Low-level input current VIL = 0 –5 5 µA
DIGITAL INPUT TIMING
tHIGH RESET pin held high for device reset 25 ns
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
See the applications section of Power Supply Recommendations for ICC for specific part configuration and how to calculate ICC for a specific design.
To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Assured by characterization.
This parameter is programmable.
Assured by characterization. ATE tested at 122.88 MHz.
FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) – 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –55°C to 105°C without violating specifications.
VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.
Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
LVPECL uses a 120-Ω emitter resistor, LVDS and HSDS use a 560-Ω shunt.
Assured by characterization. ATE tested to 10 MHz.
Assumes OSCin has 50% input duty cycle.
Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
20 MHz

SPI Interface Timing

MIN NOM MAX UNIT
tds Setup time for SDI edge to SCLK rising edge See Figure 1 10 ns
tdH Hold time for SDI edge from SCLK rising edge See Figure 1 10 ns
tSCLK Period of SCLK See Figure 1 50(19) ns
tHIGH High width of SCLK See Figure 1 25 ns
tLOW Low width of SCLK See Figure 1 25 ns
tcs Setup time for CS* falling edge to SCLK rising edge See Figure 1 10 ns
tcH Hold time for CS* rising edge from SCLK rising edge See Figure 1 30 ns
tdv SCLK falling edge to valid read back data See Figure 1 20 ns

Timing Diagram

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming.

4-wire mode read back has the same timing as the SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 is written as 0.

LMK04828-EP 30189003.gif Figure 1. SPI Timing Diagram

Typical Characteristics – Clock Output AC Characteristics

NOTE: These plots show performance at frequencies beyond the point at which the part is ensured to operate in order to give an idea of the capabilities of the part. They do not imply any sort of ensured specification.
For Figure 2 and Figure 3, CLKout2_3_IDL=1; CLKout2_3_ODL=0; LVPECL20 with 240-Ω emitter resistors; DCLKout2 Frequency = 245.76 MHz; DCLKout2_MUX = 0 (Divider). Balun is ADT2-1T+.
LMK04828-EP tc_lmk04828b_automate_data,LMK04828b-1013-27,245.76 MHz, CLKout2 LVPECL20, Div10, MuxDivider, IDL1, ODL0_pndata_CLKout2_ADT21T_VCO0.png
VCO_MUX = 0 (VCO0) PLL2 Loop Filter Bandwidth = 344 kHz
VCO0 = 2457.6 MHz PLL2 Phase Margin = 73°
DCLKout2_DIV = 10
Figure 2. LMK04828-EP DCLKout2 Phase Noise
LMK04828-EP tc_lmk04828b_automate_data,LMK04828b-1013-27,245.76 MHz, CLKout2 LVPECL20, Div12, MuxDivider, IDL1, ODL0_pndata_CLKout2_ADT21T_VCO1.png
VCO_MUX = 1 (VCO1) PLL2 Loop Filter Bandwidth = 233 kHz
VCO = 2949.12 MHz PLL2 Phase Margin = 70°
DCLKout2_DIV = 12
Figure 3. LMK04828-EP DCLKout2 Phase Noise