SNAS703 April   2017 LMK04828-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Timing Diagram
    8. 7.8 Typical Characteristics - Clock Output AC Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1  Jitter Cleaning
      2. 9.1.2  JEDEC JESD204B Support
      3. 9.1.3  Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
      4. 9.1.4  VCXO or Crystal Buffered Output
      5. 9.1.5  Frequency Holdover
      6. 9.1.6  PLL2 Integrated Loop Filter Poles
      7. 9.1.7  Internal VCOs
      8. 9.1.8  External VCO Mode
      9. 9.1.9  Clock Distribution
        1. 9.1.9.1 Device Clock Divider
        2. 9.1.9.2 SYSREF Clock Divider
        3. 9.1.9.3 Device Clock Delay
        4. 9.1.9.4 SYSREF Delay
        5. 9.1.9.5 Glitchless Half Step and Glitchless Analog Delay
        6. 9.1.9.6 Programmable Output Formats
        7. 9.1.9.7 Clock Output Synchronization
      10. 9.1.10 0-Delay
      11. 9.1.11 Status Pins
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How To Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
        2. 9.3.3.2 Dynamic Digital Delay
        3. 9.3.3.3 Single and Multiple Dynamic Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
      6. 9.3.6 Digital Lock Detect
        1. 9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 During Holdover
        3. 9.3.7.3 Exiting Holdover
        4. 9.3.7.4 Holdover Frequency Accuracy and DAC Performance
        5. 9.3.7.5 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Device Functional Modes
      1. 9.4.1 DUAL PLL
      2. 9.4.2 0-DELAY Dual PLL
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 SPI LOCK
        2. 9.5.1.2 SYSREF_CLR
    6. 9.6 Register Maps
      1. 9.6.1 Register Map for Device Programming
    7. 9.7 Device Register Descriptions
      1. 9.7.1 System Functions
        1. 9.7.1.1 RESET, SPI_3WIRE_DIS
        2. 9.7.1.2 POWERDOWN
        3. 9.7.1.3 ID_DEVICE_TYPE
        4. 9.7.1.4 ID_PROD[15:8], ID_PROD
        5. 9.7.1.5 ID_MASKREV
        6. 9.7.1.6 ID_VNDR[15:8], ID_VNDR
      2. 9.7.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
        1. 9.7.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
        2. 9.7.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
        3. 9.7.2.3 DCLKoutX_DDLYd_CNTH, DCLKoutX_DDLYd_CNTL
        4. 9.7.2.4 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
        5. 9.7.2.5 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
        6. 9.7.2.6 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
        7. 9.7.2.7 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
        8. 9.7.2.8 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
      3. 9.7.3 SYSREF, SYNC, and Device Config
        1. 9.7.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
        2. 9.7.3.2  SYSREF_CLKin0_MUX, SYSREF_MUX
        3. 9.7.3.3  SYSREF_DIV[12:8], SYSREF_DIV[7:0]
        4. 9.7.3.4  SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
        5. 9.7.3.5  SYSREF_PULSE_CNT
        6. 9.7.3.6  PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
        7. 9.7.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
        8. 9.7.3.8  DDLYd_SYSREF_EN, DDLYdX_EN
        9. 9.7.3.9  DDLYd_STEP_CNT
        10. 9.7.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
        11. 9.7.3.11 SYNC_DISSYSREF, SYNC_DISX
        12. 9.7.3.12 Fixed Register
      4. 9.7.4 (0x146 - 0x149) CLKin Control
        1. 9.7.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
        2. 9.7.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
        3. 9.7.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
        4. 9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
      5. 9.7.5 RESET_MUX, RESET_TYPE
      6. 9.7.6 (0x14B - 0x152) Holdover
        1. 9.7.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
        2. 9.7.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
        3. 9.7.6.3 DAC_TRIP_LOW
        4. 9.7.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
        5. 9.7.6.5 DAC_CLK_CNTR
        6. 9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
        7. 9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
      7. 9.7.7 (0x153 - 0x15F) PLL1 Configuration
        1. 9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
        2. 9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
        3. 9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
        4. 9.7.7.4 PLL1_N
        5. 9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
        6. 9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
        7. 9.7.7.7 PLL1_R_DLY, PLL1_N_DLY
        8. 9.7.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
      8. 9.7.8 (0x160 - 0x16E) PLL2 Configuration
        1. 9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
        2. 9.7.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
        3. 9.7.8.3 PLL2_N_CAL
        4. 9.7.8.4 PLL2_FCAL_DIS, PLL2_N
        5. 9.7.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
        6. 9.7.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
        7. 9.7.8.7 PLL2_LF_R4, PLL2_LF_R3
        8. 9.7.8.8 PLL2_LF_C4, PLL2_LF_C3
        9. 9.7.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
      9. 9.7.9 (0x16F - 0x1FFF) Misc Registers
        1. 9.7.9.1  Fixed Register 0x171
        2. 9.7.9.2  Fixed Register 0x172
        3. 9.7.9.3  PLL2_PRE_PD, PLL2_PD
        4. 9.7.9.4  OPT_REG_1
        5. 9.7.9.5  OPT_REG_2
        6. 9.7.9.6  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
        7. 9.7.9.7  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
        8. 9.7.9.8  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
        9. 9.7.9.9  RB_DAC_VALUE
        10. 9.7.9.10 RB_HOLDOVER
        11. 9.7.9.11 SPI_LOCK
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
      2. 10.1.2 Driving CLKin and OSCin Inputs
        1. 10.1.2.1 Driving CLKin Pins With a Differential Source
        2. 10.1.2.2 Driving CLKin or OSCin Pins With a Single-Ended Source
      3. 10.1.3 Using AC-Coupled Clock Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Clock Architect
          2. 10.2.2.1.2 Clock Design Tool
        2. 10.2.2.2 Device Configuration and Simulation
        3. 10.2.2.3 Device Programming
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Clock Architect
        2. 13.1.1.2 Clock Design Tool
        3. 13.1.1.3 TICS Pro
      2. 13.6   Electrostatic Discharge Caution
      3. 13.7   Glossary
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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11 Power Supply Recommendations

11.1 Current Consumption / Power Dissipation Calculations

From Table 85 the current consumption can be calculated for any configuration. Data below is typical and not assured.

Table 85. Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V)

BLOCK TEST CONDITIONS TYPICAL ICC
(mA)		 POWER
DISSIPATED
in DEVICE
(mW)		 POWER
DISSIPATED
EXTERNALLY
(mW)
CORE AND FUNCTIONAL BLOCKS
Core Dual Loop, Internal VCO0 PLL1 and PLL2 locked 131.5 433.95 —
VCO VCO1 is selected LMK04828-EP 13.5 44.55 —
OSCin Doubler Doubler is enabled EN_PLL2_REF_2X = 1 3 9.9 —
CLKin Any one of the CLKinX is enabled 4.9 16.17 —
Holdover Holdover is enabled HOLDOVER_EN = 1 1.3 4.29 —
Hitless switch is enabled HOLDOVER_HITLESS_SWITCH = 1 0.9 2.97 —
Track mode TRACK_EN = 1 2.5 8.25 —
SYNC_EN = 1 Required for SYNC and SYSREF functionality 7.6 25.08 —
SYSREF Enabled SYSREF_PD = 0 27.2 89.76 —
Dynamic Digital Delay enabled SYSREF_DDLY_PD = 0 5 16.5 —
Pulser is enabled SYSREF_PLSR_PD = 0 4.1 13.53
SYSREF Pulses mode SYSREF_MUX = 2 3 9.9
SYSREF Continuous mode SYSREF_MUX = 3 3 9.9
CLOCK GROUP
Enabled Any one of the CLKoutX_Y_PD = 0 20.1 66.33
IDL Any one of the CLKoutX_Y_IDL = 1 2.2 7.26
ODL Andy one of the CLKoutX_Y_ODL = 1 3.2 10.56
Clock Divider Divider Only DCLKoutX_MUX = 0 13.6 44.88
Divider + DCC + HS DCLKoutX_MUX = 1 17.7 58.41
Analog Delay + Divider DCLKoutX_MUX = 3 13.6 44.88
CLOCK OUTPUT BUFFERS
LVDS 100 Ω differential termination 6 19.8 —
HSDS HSDS 6 mA, 100 Ω differential termination 8.8 29.04 —
HSDS 8 mA, 100 Ω differential termination 11.6 38.28 —
HSDS 10 mA, 100-Ω differential termination 19.4 64.02 —
OSCout BUFFERS
LVDS 100-Ω differential termination 18.5 61.05 —
LVCMOS LVCMOS Pair 150 MHz 42.6 140.58 —
LVCMOS Single 150 MHz 27 89.1 —