ZHCSHU9K September   2011  – December 2023 LMK03806

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 描述
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Features Description
      1. 7.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 7.3.2 Crystal Support With Buffered Outputs
      3. 7.3.3 Integrated Loop Filter Poles
      4. 7.3.4 Integrated VCO
      5. 7.3.5 Clock Distribution
        1. 7.3.5.1 CLKout DIvider
        2. 7.3.5.2 Programmable Output Type
        3. 7.3.5.3 Clock Output Synchronization
      6. 7.3.6 Default Start-Up Clocks
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 General Information
        1. 7.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 7.5.1.2 Recommended Initial Programming Sequence
        3. 7.5.1.3 READBACK
          1. 7.5.1.3.1 Readback Example
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Crystal Interface
      2. 8.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 8.1.3 Driving OSCin Pins With a Differential Source
      4. 8.1.4 Frequency Planning With the LMK03806
      5. 8.1.5 Configuring the PLL
        1. 8.1.5.1 Example PLL Configuration
      6. 8.1.6 Digital Lock Detect
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
          1. 8.2.2.1.1 Clock Architect
          2. 8.2.2.1.2 Clock Design Tool
          3. 8.2.2.1.3 Calculation Using LCM
        2. 8.2.2.2 Device Configuration
        3. 8.2.2.3 PLL Loop Filter Design
          1. 8.2.2.3.1 Example Loop Filter Design
        4. 8.2.2.4 Other Device Specific Configuration
          1. 8.2.2.4.1 Digital Lock Detect
        5. 8.2.2.5 Device Programming
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 System Level Diagram
    4. 8.4 Best Design Practices
      1. 8.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 8.4.2 LVPECL Outputs
      3. 8.4.3 Sharing MICROWIRE (SPI) Lines
      4. 8.4.4 SYNC Pin
      5. 8.4.5 CLKout Vcc Pins
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Current Consumption and Power Dissipation Calculations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Register Maps
    1. 10.1  Default Device Register Settings After Power On Reset
    2. 10.2  Register R0 TO R5
      1. 10.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
      2. 10.2.2 RESET
      3. 10.2.3 POWERDOWN
      4. 10.2.4 CLKoutX_Y_DIV, Clock Output Divide
    3. 10.3  Registers R6 TO R8
      1. 10.3.1 CLKoutX_TYPE
    4. 10.4  REGISTER R9
    5. 10.5  REGISTER R10
      1. 10.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
      2. 10.5.2 OSCout0_TYPE
      3. 10.5.3 EN_OSCoutX, OSCout Output Enable
      4. 10.5.4 OSCoutX_MUX, Clock Output Mux
      5. 10.5.5 OSCout_DIV, Oscillator Output Divide
    6. 10.6  REGISTER R11
      1. 10.6.1 NO_SYNC_CLKoutX_Y
      2. 10.6.2 SYNC_POL_INV
      3. 10.6.3 SYNC_TYPE
      4. 10.6.4 EN_PLL_XTAL
    7. 10.7  REGISTER R12
      1. 10.7.1 LD_MUX
      2. 10.7.2 LD_TYPE
      3. 10.7.3 SYNC_PLL_DLD
    8. 10.8  REGISTER R13
      1. 10.8.1 READBACK_TYPE
      2. 10.8.2 GPout0
    9. 10.9  REGISTER 14
      1. 10.9.1 GPout1
    10. 10.10 REGISTER 16
    11. 10.11 REGISTER 24
      1. 10.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
      2. 10.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
      3. 10.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
      4. 10.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
    12. 10.12 REGISTER 26
      1. 10.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
      2. 10.12.2 PLL_CP_GAIN, PLL Charge Pump Current
      3. 10.12.3 PLL_DLD_CNT
    13. 10.13 REGISTER 28
      1. 10.13.1 PLL_R, PLL R Divider
    14. 10.14 REGISTER 29
      1. 10.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
      2. 10.14.2 PLL_N_CAL, PLL N Calibration Divider
    15. 10.15 REGISTER 30
      1. 10.15.1 PLL_P, PLL N Prescaler Divider
      2. 10.15.2 PLL_N, PLL N Divider
    16. 10.16 REGISTER 31
      1. 10.16.1 READBACK_ADDR
      2. 10.16.2 uWire_LOCK
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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10.1 Default Device Register Settings After Power On Reset

Table 10-2 shows the default register settings programmed in silicon for the LMK03806 after power on or asserting the reset bit. Capital X and Y represent numeric values.

Table 10-2 Default Device Register Settings After Power On/Reset
GROUPFIELD NAMEDEFAULT VALUE (DECIMAL)DEFAULT
STATE		FIELD DESCRIPTIONREGISTERBIT LOCATION (MSB:LSB)
Clock Output ControlCLKout0_1_PD1PDPowerdown control for divider, and both output buffersR031
CLKout2_3_PD1PDR1
CLKout4_5_PD1PDR2
CLKout6_7_PD0NormalR3
CLKout8_9_PD0NormalR4
CLKout10_11_PD1PDR5
RESET0Not in resetPerforms power on reset for deviceR017
POWERDOWN0Disabled
(device is active)		Device power down controlR117
CLKout0_1_DIV25Divide-by-25Divide for clock outputsR015:5 [11]
CLKout2_3_DIV25Divide-by-25R1
CLKout4_5_DIV25Divide-by-25R2
CLKout6_7_DIV(1)1Divide-by-1R3
CLKout8_9_DIV25Divide-by-25R4
CLKout10_11_DIV25Divide-by-25R5
CLKout3_TYPE0PowerdownIndividual clock output format. Select from LVDS/LVPECL/LVCMOS.R631:28 [4]
CLKout7_TYPE0PowerdownR7
CLKout11_TYPE0PowerdownR8
CLKout2_TYPE0PowerdownR627:24 [4]
CLKout6_TYPE(1)8LVCMOS
(Norm/Norm)		R7
CLKout10_TYPE0PowerdownR8
CLKout1_TYPE0PowerdownR623:20 [4]
CLKout5_TYPE0PowerdownR7
CLKout9_TYPE0PowerdownR8
CLKout0_TYPE0PowerdownR619:16 [4]
CLKout4_TYPE0PowerdownR7
CLKout8_TYPE1LVDSR8
Osc Buffer Control ModeOSCout1_TYPE21600 mVpp LVPECLSet LVPECL amplitudeR1031:30 [2]
OSCout0_TYPE1LVDSOSCout0 default clock outputR1027:24 [4]
EN_OSCout10DisabledDisable OSCout1 output bufferR1023
EN_OSCout01EnabledEnable OSCout0 output bufferR1022
OSCout1_MUX0Bypass DividerSelect OSCout divider for OSCout1 or bypassR1021
OSCout0_MUX0Bypass DividerSelect OSCout divider for OSCout0 or bypassR1020
OSCout_DIV0Divide-by-8OSCout divider valueR1018:16 [3]
SYNC ControlNO_SYNC_CLKout10_110Will syncDisable individual clock groups from becoming synchronized.R1125
NO_SYNC_CLKout8_91Will not syncR1124
NO_SYNC_CLKout6_71Will not syncR1123
NO_SYNC_CLKout4_50Will syncR1122
NO_SYNC_CLKout2_30Will syncR1121
NO_SYNC_CLKout0_10Will syncR1120
SYNC_POL_INV1Logic LowSets the polarity of the SYNC pin when input. (Use for software SYNC)R1116
SYNC_TYPE1Input /w
Pull-up		SYNC IO pin typeR1113:12 [2]
Other Mode ControlEN_PLL_XTAL0DisabledEnable Crystal oscillator for OSCinR115
LD_MUX3ReservedFtest/LD pin selection when outputR1231:27 [5]
LD_TYPE3Output
(Push-Pull)		LD IO pin typeR1226:24 [3]
SYNC_PLL_DLD0No effectWhen set, force SYNC until PLL locksR1223
READBACK_TYPE3Output (Push-Pull)Readback Pin TypeR1326:24 [3]
GPoutGPout02Weak pull-downGPout0 output stateR1318:16 [3]
GPout12Weak pull-downGPout1 output stateR1428:26 [3]
PLL ControlPLL_C4_LF010 pFPLL integrated capacitor C4 valueR2431:28 [4]
PLL_C3_LF010 pFPLL integrated capacitor C3 valueR2427:24 [4]
PLL_R4_LF0200 ΩPLL integrated resistor R4 valueR2422:20 [3]
PLL_R3_LF0200 ΩPLL integrated resistor R3 valueR2418:16 [3]
EN_PLL_REF_2X0Disabled, 1xDoubles reference frequency of PLL.R2629
PLL_CP_GAIN33.2 mAPLL Charge Pump GainR2627:26 [2]
PLL_DLD_CNT81928192 CountsNumber of PDF cycles which phase error must be within DLD window before LD state is asserted.R2619:6 [14]
PLL_R4Divide-by-4PLL R Divider (1 to 4095)R2831:20 [12]
OSCin_FREQ7448 to 500 MHzOSCin frequency rangeR2926:24 [3]
PLL_N_CAL48Divide-by-48Must be programmed to PLL_N value.R2922:5 [18]
PLL_P2Divide-by-2PLL N Divider Prescaler (2 to 8)R3026:24 [3]
PLL_N48Divide-by-48PLL N Divider (1 to 262143)R3022:5 [18]
uWireuWire_LOCK0WritableThe values of registers R0 to R30 are lockableR315
(1) On POR, any output from CLKout6 cannot be used. R3 must be programmed per data sheet specifications before CLKout6 can be used.