Table 5. Oscilloscope Example Including Front-End Attenuators

8.2.1.2.1 Settings and ADC SPI Code (ECM)

Covering the range from 1 mV/DIV to 10 V/DIV requires the following adjustment within the digital oscilloscope:

• Front-end attenuator
• LMH6518 preamp
• LMH6518 ladder attenuation
• ADC FS value (ECM)

The LMH6518 product folder contains a spreadsheet which allows one to calculate the front-end attenuator, LMH6518 preamp gain (HG or LG), ladder attenuation, and ADC FS setting based on the scope vertical scale
(S in V/DIV).

Here is the step-by-step procedure that explains the operations performed by the said spreadsheet based on the scope vertical scale setting (S in V/div) and front-end attenuation A (from Table 5). A numerical example is also worked out for more clarification:

1. Determine the required signal path gain, K, with Equation 10:
Equation 10.

(assuming the full scale signal occupies 95% of the 0.7 V_PP FS for 5% overhead which occupies 8 vertical scope divisions).

Required condition: −2.37 dB ≤ K ≤ 40.3 dB

Example: With S = 110 mV/DIV, Table 5 shows that A = 10 V/V in Equation 11.

Equation 11.
2. Determine the LMH6518 gain, G:
   • G is the closest LMH6518 gain, to the value of K where:
   • G = (38.8 – 2n)dB; n = 0, 1, 2, …, 20
   • For this example, the closest G to K = 17.57 dB is 16.8 dB (with n = 11). The next LMH6518 gain,
     18.8 dB (with n = 10) is incorrect as 16.8 is closer. If 18.8 dB were mistakenly chosen, the ADC FS setting is out of range.
   • Therefore: G = 16.8 dB
3. Determine preamp (HG or LG) and ladder attenuation:
   • If G ≥ 18.8 dB → Preamp is HG and ladder attenuation = 38.8 – G
   • If G < 18.8 dB → Preamp is LG and ladder attenuation = 18.8 – G
   • For this example, with G = 16.8 → Preamp LG and Ladder Attenuation = 2 dB (= 18.8 to 16.8).
4. Determine the required ADC FS voltage, FS_E, with Equation 12:
Equation 12.

The 1.05 factor is to add 5% FS overhead margin to avoid ADC overdrive with Equation 13.

Equation 13.

Required condition: 0.56 V ≤ FS_E ≤ 0.84 V

Recommend condition: 0.595 V ≤ FS_E ≤ 0.805 V for optimum ADC FS

5. Determine the ADC ECM code ratio with Equation 14:
   Equation 14.
   where
   • 0.28 V = (0.84 – 0.56) V
   • 0.56 V is the lower end of the ADC FS adjustability
   • For this example:
   
   • Required condition: 0 ≤ ECM (ratio) ≤ 1
6. Determine the ECM binary code sent on ADC SPI bus:
   • Convert the ECM value represented by the ratio calculated above, to binary:
   • ECM (binary) = DEC2BIN{ECM(ratio) × 511, 9}
   • Where DEC2BIN is a spreadsheet function which converts the decimal ECM ratio, from step 5 above, multiplied by 511 distinct levels, into binary 9 bits.

   NOTE

   The Web based spreadsheet computes ECM without the use of DEC2BIN function to ease usage by all spreadsheet users who may not have this function installed.

   • For this example: ECM (binary) = DEC2BIN(0.283 × 511, 9) = 010010000. This is the number sent to the ADC on the SPI bus to program the ADC to proper FS voltage.

8.2.1.2.2 Input and Output Considerations

The LMH6518’s ideal input and output conditions, considered individually, are listed in Table 6.

In addition to the individual conditions listed in Table 6, the input and output terminal conditions must match differentially (that is, +IN to −IN and +OUT to −OUT), as well, for best performance.

The input is differential but is driven single-ended as long as the conditions of Table 6 are met, and there is good matching between the driven and undriven inputs from DC to the highest frequency of interest. If not, there is a settling time impact among other possible performance degradations. The data sheet specifications are with single-ended input, unless specified. Figure 61 is the recommended bench-test schematic to drive one input and to bias the other input with good matching in mind.

Figure 61. Recommended Single-Ended Bench-Test Input Drive from 50-Ω Source

With Figure 61, each LMH6518 input sees 25 Ω to ground at higher frequencies when the capacitors look like shorts. This impedance increases to 125 Ω at DC for both inputs, thereby preserving the required matching at any frequency. This configuration, using properly selected R’s and C’s, allows four times less biasing power dissipation than when undriven inputs are biased with an effective 25 Ω from the LMH6518 input to ground.

It is possible to drive the LMH6518 input from a ground-referenced, 50-Ω source by providing level shift circuitry on the driven input. Figure 62 shows a circuit where half the input signal reaches the LMH6518 input while the negative supply voltage (V_EE) ensures that the 50Ω source at J1 does not experience any biasing current while providing 50-Ω termination to the source. The driven input (+IN) is biased to 2.5 V (V_CC/2) in Figure 62.

Figure 62. LMH6518 Driven by a Ground Referenced Source

In Figure 62, the equivalent impedance from each LMH6518 input to ground is around 38 Ω. The power consumption of this configuration is approximately 0.5 W (in R₁ – R₅) which is higher than that of Figure 61 because of additional power dissipated to perform the level shifting. Additional 50-Ω attenuators is placed between J1 and R₂/R₃ junction in Figure 62 to accommodate higher input voltages.

It is also possible to shift the LMH6518 output common mode level using a level shift approach similar to that of Figure 62. The circuit in Figure 63 shows an implementation where the LMH6518’s nominal 1.2 V CM output, set by a 1.2 V on V_CM input from the Gsps ADC, is shifted lower for proper interface to different ADCs (which require V_CM = 0 V and have high input impedance).

Figure 63. Output CM Shift Scheme

In Figure 63, Vx is kept at 1.2 V by proper selection of external resistor values, so that the LMH6518 outputs are not CM-loaded. As was the case with input level shifting, this output-level shifting also consumes additional power (0.58 W).

8.2.1.2.2.1 Output Swing, Clamping, and Operation Beyond Full Scale

One of the major concerns in interfacing to low voltage ADC’s (such as the Gsps ADC that the LMH6518 is intended to drive) is ensuring that the ADC input is not violated with excessive drive. For this reason, plus the important requirement of an oscilloscope to recover quickly and gracefully from an overdrive condition, the LMH6518 is fitted with three overvoltage clamps; one at the preamp output, and one at the main and auxiliary outputs (each). The preamp clamp is responsible for preventing the preamp from saturation (to minimize recovery time) with large ladder attenuation when preamp output swing is at its highest. On the other hand, the output clamps perform this function when ladder attenuation is lower. Therefore, the output amplifier is closer to saturation and prolonged recovery (if not properly clamped). The combination of these clamps results in Figure 50, Figure 51, Figure 52, and Figure 66. With these four graphs, it is possible to observe where output limiting starts due to the clamp action. LMH6518 owes its fast recovery time (<5 ns) from 50% overdrive to the said clamps.

Figure 50, Figure 51, Figure 52, and Figure 66 in Typical Characteristics is used to determine the LMH6518 linear swing beyond full scale. This information sets the overdrive limit for both oscilloscope waveform capture and signal triggering. The preamp clamp is set tighter than the output clamp, evidenced by lower output swing with 20-dB ladder attenuation than with 0 dB. With high ladder attenuation (20 dB) defining the limit, the graphs show that the +OUT and −OUT difference of 0.4 V is well inside the clamp range, thereby ensuring 0.8 V_PP of unhindered output swing. This corresponds to an overdrive capability of approximately ±7% beyond full scale.

From Figure 58, the signal path consists of the input impedance switch, the attenuator switch, low noise amplifier (LNA, JFET amplifier) to drive the LMH6518 input (+IN), and the DAC to provide offset adjust. The LNA must have the following characteristics:

• Set U1’s common mode level to V_CC/2 (approximately 2.5 V)
• Low drift (1 mV shift at LNA output could translate into 88 mV shift at LMH6518 output at maximum gain, or approximately 13% of FS)
• Low output impedance (≤ 50 Ω) to drive U1 for good settling behavior
• Low noise (<0.98 nV/√Hz) to reduce the impact on the LMH6518 noise figure. Note that Figure 58 does not show the necessary capacitors across the resistors in the front-end attenuators (see Figure 69). These capacitors provide frequency response compensation and limit the noise contribution from the resistors so that they do not impact the signal path noise. For more information about front-end attenuator design, including frequency compensation, see Related Documentation for additional resources.
• Gain of 1 V/V (or close to 1 V/V)
• Excellent frequency response flatness from DC to >500 MHz to 800 MHz to not impact the time domain performance

The undriven input (−IN) is biased to V_CC/2 using a voltage driver. The impedance driving the LMH6518’s −IN must be closely matched to the LNA’s output impedance for good settling time performance.

JFET LNA Implementation shows one possible implementation of the LNA buffer along with performance data.

When the LMH6518’s auxiliary output is not used, it is possible to disable this output using SPI-1 (see Logic Functions for SPI register map). Electrical Characteristics shows that by doing so, device power dissipation decreases by the reduction in supply current of about 60 mA. As seen in Figure 64, in the absence of heavy common loading, the auxiliary output is at a voltage close to 1.7 V (V_CC = 5 V). With higher supply voltages, the auxiliary voltage also increases. It is important to ensure any circuitry tied to this output is capable of handling the 2.3 V possible under V_CC worst case condition of 5.5 V.

Figure 64. Auxiliary Output Voltage as a Function of V_CC

8.2.1.2.3 Oscilloscope Trigger Applications

With the Auxiliary output of the LMH6518 offering a second output that follows the main one (except for a slightly reduced distortion performance), the oscilloscope trigger function is implemented by tapping this output. The auxiliary common mode is set with the V_{CM_Aux} input of the LMH6518. If required, the trigger function is placed at a distance from the main signal path by taking advantage of the differential auxiliary output and rejecting any board related common mode interference pick-up at the receive end.

If trigger circuitry is physically close to the LMH6518, the circuit diagram shown in Figure 65 allows operation using only one of two auxiliary outputs. Unused outputs require proper termination using R₁, R₁₁ combination. U3 (DAC101C085) generates a 0- 2.5 V trigger level, with 2.4 mV resolution as in Equation 15 or 0.7%
(= 2.4 mV × 100/0.35 V_PP) of FS, which is compared to the LMH6518 +OUT AUX by using an ultra-fast comparator, U2 (LMH7220). U2’s complimentary LVDS output is terminated in the required 100-Ω load (R₁₀), for best performance, where the LVDS trigger output is available.

Equation 15.

The LMH7220’s offset voltage (±9.5 mV) and offset voltage drift (±50 µV/°C) error is 5.9 LSB of the trigger DAC (U3) as in Equation 16.

Equation 16.

The offset voltage related portion of this error is nulled-out, if necessary, during the oscilloscope initial calibration. To do so, the LMH6518 input is terminated properly with no input applied and U3 output is adjusted around V_{CM_Aux} voltage (1.2 V ±10 mV) while looking for U2’s output transition. U3’s output, relative to V_{CM_Aux} at transition corresponds to U2’s offset error which is factored into the trigger readings and thus eliminated, leaving only the offset voltage temperature drift component (= 2 LSB).

Figure 65. Single-Ended Trigger from LMH6518 Auxiliary Output

U2’s minimum toggle rate specification of 750 Mb/s with ±50 mV overdrive allow the oscilloscope to trigger on repetitive waveforms well above the 500 MHz oscilloscope bandwidth applications, when the input signal is at least 14.3% of FS swing with Equation 17.

Equation 17.

The worst case single event minimum discernable pulse width is set by the LMH7220’s propagation delay specification of 3.63 ns (20 mV overdrive).

Both the main and the auxiliary outputs recover gracefully and quickly from a 50% overdrive condition as tabulated in Electrical Characteristics under overdrive recovery time. However, overdrive conditions beyond 50% could result in longer recovery times due to the interaction between an internal clamp and the common mode feedback loop that sets the output common mode voltage. This may have an impact on both the displayed waveform and the oscilloscope trigger. The result is a loss of trigger pulse or visual distortion of the displayed waveform. To avoid this scenario, the oscilloscope must detect an excessive overdrive and go into trigger-loss mode. Done this way, the oscilloscope display would show the last waveform that did not violate the overdrive condition. Preferably, there is a visual indicator on the screen that alerts the user of the excessive condition, and returns the display to normal once the condition is corrected.

Table 7. Suitable JFET Candidates Specifications

8.2.2.2.1 Attenuator Design

Figure 69 shows a front-end attenuator designed to work with Figure 68.

Figure 69. Front End Attenuator for JFET LNA Implementation

R_LNA and C_LNA are the input impedance components of the JFET LNA. The 10:1 and 100:1 attenuators bottom resistors (R₂ and R₄) are adjusted higher to compensate for the LNA’s 1-MΩ input impedance, compared to the case where a high-input-impedance LNA is used. The two switches used on the input and output of the attenuator block are low-capacitance, high-isolation switches to reduce any speed or crosstalk impact. C₁ to C₄ provide the proper frequency response (and step response) by creating zeros that flatten the response for wide-band operation. For the 10:1 attenuator, R₁C₁ = R₂C₂. The same applies to the 100:1 attenuator. The shunt capacitors, C₁ to C₄, have a important other benefit in that they roll-off the resistor thermal noise at a low frequency (low pass response, −3 dB down at approximately 20 kHz) thereby eliminating any significant noise contribution from the attenuation resistors. Otherwise, the channel noise is dominated by the attenuator resistor thermal noise. C₂ and C₆ trimmer capacitors are adjusted to match the input capacitance regardless of attenuator used.