SNOSB21D Data sheet | 德州仪器 TI.com.cn

SNOSB21D May 2008 – September 2016 LMH6518

PRODUCTION DATA.

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RGH|16
- MPQF182A

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_CC (5 V nominal)		5.5	V
Supply voltage	V_DD (3.3 V nominal)		3.6	V
Differential input			±1	V
Input common mode voltage		1	4	V
V_CM and V_{CM_Aux}			2	V
SPI inputs			3.6	V
Soldering temperature	Infrared or convention (20 s)		235	°C
Soldering temperature	Wave (10 s)		260	°C
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine model (MM)	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Analog supply voltage		5 ±5%		V
V_DD	Digital supply voltage		3.3 ±5%		V
T_A	Temperature range	–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMH6518	UNIT
		RGH (WQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	40	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31.7	°C/W
R_θJB	Junction-to-board thermal resistance	11.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	11.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise noted, all limits are ensured for T_A = 25°C, input CM = 2.5 V, V_CM = 1.2 V, V_{CM_Aux} = 1.2 V, single-ended input drive, V_CC = 5 V, V_DD = 3.3 V, R_L = 100 Ω differential (both main and auxiliary outputs), V_OUT = 0.7 V_PP differential (both main and auxiliary outputs), both main and auxiliary output specifications, full bandwidth setting, gain = 18.8 dB (preamp LG, 0 dB ladder attenuation), and full power setting (with auxiliary output turned on) (see Table 8 for abbreviations used).⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN⁽²⁾	TYP⁽³⁾	MAX⁽²⁾	UNIT
DYNAMIC PERFORMANCE
LSBW	–3-dB bandwidth	All gains			900		MHz
	Peaking	All gains			1		dB
GF_0.1 dB	±0.1-dB gain flatness	All gains			150		MHz
GF_1 dB	±1-dB gain flatness	All gains			400		MHz
TRS	Rise time				460		ps
TRL	Fall time				450
OS	Overshoot	Main output			9%
t_{s_1}	Settling time	Main output, ±0.5%			10		ns
t_{s_2}	Settling time	Main output, ±0.05%			14
t_recover	Recovery time⁽⁴⁾	All gains			<5		ns
P_D	Propagation delay	V_OUT = 0.7 V_PP, all gains			1.2		ns
P_{D_VAR}	Propagation delay variation	Gain varied			100		ps
NOISE, DISTORTION, AND RF SPECIFICATIONS
e_{n_1}	Input noise spectral density	Max gain, 10 MHz			0.98		nV/√Hz
e_{n_2}	Input noise spectral density	Preamp LG and 0-dB ladder, 10 MHz			4.1		nV/√Hz
e_{no_1}	RMS output noise	Max gain, 100 Hz to 400 MHz			1.7		mV
e_{no_2}	RMS output noise	Preamp LG, 0-dB ladder, 100 Hz to 400 MHz			940		µV
NF_1	Noise figure	Max gain, R_S = 50 Ω each input, 10 MHz			3.8		dB
NF_2	Noise figure	Preamp LG, 0-dB ladder, R_S = 50 Ω each input, 10 MHz			13.5		dB
HD2_1	2^nd harmonic distortion⁽⁵⁾	Main output, 100 MHz, all gains			–50		dBc
HD3_1	3^rd harmonic distortion⁽⁵⁾	Main output, 100 MHz, all gains			–53		dBc
HD2_2	2^nd harmonic distortion⁽⁵⁾	Auxiliary output, 100 MHz, all gains			–48		dBc
HD3_2	3^rd harmonic distortion⁽⁵⁾	Auxiliary output, 100 MHz, all gains			–50		dBc
HD2_3	2^nd harmonic distortion⁽⁵⁾	Main output, 250 MHz, all gains			–44		dBc
HD3_3	3^rd harmonic distortion⁽⁵⁾	Main output, 250 MHz, all gains			–50		dBc
HD2/HD3_4	2^nd/ 3^rd harmonic distortion⁽⁵⁾	Auxiliary output, 250 MHz, all gains			–42		dBc
IMD3	Intermodulation distortion⁽⁵⁾	f = 250 MHz, main output			–65		dBc
OIP3_1	Intermodulation intercept⁽⁵⁾	Main output, 250 MHz			26		dBm
P_1dB_main	–1-dB compression	Main output, 250 MHz, 0-dB ladder			1.8		V_PP
P_1dB_main	–1-dB compression	Main output, 250 MHz, 20-dB ladder			1		V_PP
P_1dB_aux	–1-dB compression	Auxiliary output, 250 MHz, 0-dB ladder			1.65		V_PP
P_1dB_aux	–1-dB compression	Auxiliary output, 250 MHz, 20-dB ladder			1		V_PP
GAIN PARAMETERS
A_{V_DIFF_MAX}	Maximum gain			38.1	38.8	39.5	dB
A_{V_DIFF_MIN}	Minimum gain			–1.91	–1.16	–0.4	dB
Gain_Step	Gain step size	All gains including preamp step		1.8	2	2.2	dB
Gain_Step	Gain step size with ADC (see Application and Implementation)	ADC FS adjusted			8.5		mdB
Gain_Range	Gain range			39	40	41	dB
TC_A_{V_DIFF}	Gain temp coefficient⁽⁶⁾	All gains			–0.8		mdB/°C
Gain_A_CC	Absolute gain accuracy	Compared to theoretical from max gain in 2-dB steps		0.75		0.75	dB
MATCHING
Gain_match	Gain matching, main and auxiliary	All gains			±0.1	±0.2	dB
BW_match	–3-dB bandwidth matching, main and auxiliary	All gains			5%
RT_match	Rise time matching, main and auxiliary	All gains			5%
PD_match	Propagation delay matching, main and auxiliary	All gains			100		ps
ANALOG I/O
CMRR_1	CM rejection ratio (see Table 8)	Preamp HG, 0-dB ladder, 1.9 V < CMVR < 3.1 V		45	86		dB
CMRR_2	CM rejection ratio (see Table 8)	Preamp LG, 0-dB ladder, 1.9 V < CMVR < 3.1 V		40	55		dB
CMVR_1	Input common mode voltage range	Preamp HG, all ladder steps, CMRR ≥ 45 dB		1.9		3.1	V
CMVR_2	Input common mode voltage range	Preamp LG, all ladder steps, CMRR ≥ 40 dB		1.9		3.1	V
\|ΔV_{O_CM}\|Δ_{I_CM}\|		All gains, 2 V < CMVR < 3 V		–60	–100		dB
CMRR_CM	CM rejection ratio relative to VCM (see Table 8)	Preamp LG, 0 dB			101		dB
Z_{in_diff}	Differential input impedance	All gains			150 \|\| 1.5		KΩ \|\| pF
Z_{in_CM}	CM input impedance	Preamp HG			420 \|\| 1.7		KΩ \|\| pF
Z_{in_CM}	CM input impedance	Preamp LG			900 \|\| 1.7		KΩ \|\| pF
FS_OUT1	Full scale voltage swing	Main output, all gains, THD at 100 MHz ≤ –40 dBc		770⁽⁷⁾	800		mV_PP
FS_OUT2	Full scale voltage swing	Main output, clamped, 0-dB ladder			1800	1960	mV_PP
FS_OUT3	Full scale voltage swing	Auxiliary output, all gains THD at 100 MHz ≤ –40 dBc		770⁽⁷⁾	800		mV_PP
FS_OUT4	Full scale voltage swing	Auxiliary output, clamped, 0-dB ladder			1600	1760	mV_PP
V_{OUT_MAX1}	Voltage at each output pin (clamped)	Main output, all gains, V_CM = 1.2 V		0.5		1.8	V
V_{OUT_MAX2}	Voltage at each output pin (clamped)	Auxiliary output, all gains, V_CM = 1.2 V		0.8		2.2	V
V_{OUT_MAX3}	Voltage at each output pin (clamped)	Main output, all gains, V_CM= 1.45 V				2.05	V
V_{OUT_MAX4}	Voltage at each output pin (clamped)	Auxiliary output, all gains, V_CM = 1.45 V				2.45	V
Z_{OUT_DIFF}	Differential output impedance	All gains		92	100	108	Ω
V_OOS	Output offset voltage	All gains			±15	±40	mV
V_{OOS_shift1}	Output offset voltage shift	Preamp LG to preamp HG			13.7		mV
V_{OOS_shift2}	Output offset voltage shift	All gains, excluding preamp step			12.7		mV
TCV_OOS	Output offset voltage drift⁽⁶⁾	Preamp HG, 0-dB ladder			–24		µV/°C
TCV_OOS	Output offset voltage drift⁽⁶⁾	Preamp LG, 0-dB ladder			–7		µV/°C
I_B	Input bias current⁽⁸⁾	T_A = –40°C to 85°C			40	100	µA
I_B	Input bias current⁽⁸⁾	T_A = –65°C to 150°C				140	µA
V_OCM	Output CM voltage	All gains	T_A = –40°C to 85°C		1.2		V
V_OCM	Output CM voltage	All gains	T_A = –65°C to 150°C	0.95		1.45	V
V_{OS_CM}	Output CM offset	All gains			±15	±30	mV
TC_V_{OS_CM}	CM offset voltage temperature coefficient	All gains			+55		µV/°C
BAL_Error_DC	Output gain balance error				–78		dB
BAL_Error_AC	Output gain balance error				–45		dB
PB	Phase balance error (see Table 8)	250 MHz			±0.8		deg
PSRR	Differential power supply rejection (see Table 8)	Preamp HG, 0-dB ladder		–60	–87		dB
PSRR	Differential power supply rejection (see Table 8)	Preamp LG, 0-dB ladder		–50	–70		dB
PSRR_CM	CM power supply rejection (see Table 8)	Preamp LG, 0-dB ladder		–55	–71		dB
V_{CM_I}	V_CM input bias current⁽⁸⁾	All gains	T_A = –40°C to 85°C		±1	±10	nA
V_{CM_I}	V_CM input bias current⁽⁸⁾	All gains	T_A = –65°C to 150°C			±20	nA
V_{CM_AUX_I}	V_{CM_AUX} input bias current⁽⁸⁾	All gains	T_A = –40°C to 85°C		±1	±10	nA
V_{CM_AUX_I}	V_{CM_AUX} input bias current⁽⁸⁾	All gains	T_A = –65°C to 150°C			±20	nA
DIGITAL I/O
V_IH	Input logic high	T_A = –65°C to 150°C		V_DD–0.6			V
V_IL	Input logic low	T_A = –65°C to 150°C				0.5	V
V_OH	Output logic high				V_DD		V
V_OL	Output logic low				0		V
R_{Hi_Z}	Output resistance	High impedance mode			5		MΩ
I_in	Input bias current				<1		µA
F_SCLK	SCLK rate					10	MHz
F_{SCLK_DT}	SCLK duty cyle			45%	50%	55%
POWER REQUIREMENTS
I_S1	Supply current, V_CC	T_A = –40°C to 85°C		195	210	225	mA
I_S1	Supply current, V_CC	T_A = –65°C to 150°C				230	mA
I_{S1_off}	Supply current, V_CC aux off	T_A = –40°C to 85°C			150	165	mA
I_{S1_off}	Supply current, V_CC aux off	T_A = –65°C to 150°C				170	mA
I_DD	Supply current, V_DD	T_A = –40°C to 85°C			180	350	µA
I_DD	Supply current, V_DD	T_A = –65°C to 150°C				400	µA
BANDWIDTH LIMITING FILTER SPECIFICATIONS
	Pass band tolerance, –3 dB bandwidth	All gains	20 MHz	0%	20%
			100 MHz	0%	20%
			200 MHz	0%	20%
			350 MHz		±25%
			650 MHz		±25%
			750 MHz		±25%
		Preamp LG, 0-dB ladder	350 MHz		±10%
			650 MHz		±10%
			750 MHz		±10%

(1) Electrical Characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T_J = T_A. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T_J > T_A.

(2) Limits are 100% production tested at 25°C unless otherwise specified. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material.

(4) Recovery time is the slower of the main and auxiliary outputs. Output swing of 700 mV_PP shifted up or down by 50% (0.35 V) by introducing an offset. Measured values correspond to the time it takes to return to within ±1% of 0.7 V_PP (±7 mV).

(5) Distortion data taken under single ended input condition.

(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(7) Specified by design.

(8) Positive current is current flowing into the device.

6.6 Timing Requirements

		MIN	UNIT
T_S	SDIO setup time	25	ns
T_H	SDIO hold time	25	ns
T_CES	CS enable setup time (from CS asserted to rising edge of SCLK)	25	ns
t_CDS	CS disable setup time (from CS de-asserted to rising edge of SCLK)	25	ns
T_IAG	Inter-acess gap	3	SCLK cycles

6.7 Typical Characteristics

Unless otherwise noted, input CM = 2.5 V, V_CM = 1.2 V, V_{CM AUX} = 1.2 V, single-ended input drive, V_CC = 5 V, V_DD = 3.3 V,
R_L = 100 Ω differential (both main and auxiliary outputs), V_OUT = 0.7 V_PP differential (both main and auxiliary outputs), main output specification (auxiliary is labeled), full bandwidth setting, gain = 18.8 dB (preamp LG, 0 dB ladder attenuation), and full power setting (with auxiliary output turned on).