SNOSB21D May   2008  – September 2016 LMH6518

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Preamplifier
        1. 7.3.1.1 Primary Output Amplifier
        2. 7.3.1.2 Auxiliary Amplifier
      2. 7.3.2 Overvoltage Clamp
      3. 7.3.3 Attenuator
      4. 7.3.4 Digital Control Block
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary Amplifier
      2. 7.4.2 Auxiliary Output
    5. 7.5 Programming
      1. 7.5.1 Logic Functions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Oscilloscope Front End
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Settings and ADC SPI Code (ECM)
          2. 8.2.1.2.2 Input and Output Considerations
            1. 8.2.1.2.2.1 Output Swing, Clamping, and Operation Beyond Full Scale
          3. 8.2.1.2.3 Oscilloscope Trigger Applications
        3. 8.2.1.3 Application Curves
      2. 8.2.2 JFET LNA Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Attenuator Design
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

RGH Package
16-Pin WQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 +OUT AUX O Auxiliary positive output
2 −OUT AUX O Auxiliary negative output
3, 4 VCC P Analog power supply
5, 8 GND G Ground, electrically connected to the WQFN heat sink
6 +IN I Positive input
7 –IN I Negative input
9 CS I Serial chip select (SPI interface, active low): While this signal is asserted SCLK is used to accept serial data present on SDIO and to source serial data on SDIO. When this signal is de-asserted, SDIO is ignored and SDIO is in TRI-STATE mode.
10 SDIO I/O Serial data-in or data-out (SPI interface): Serial data are shifted into the device (8 bit command and 16 bit data) on this pin while CS signal is asserted during Write operation. Serial data are shifted out of the device on this pin during a read operation while CS signal is asserted. At other times, and after one complete Access Cycle (24 bits, see Figure 54 and Figure 55), this input is ignored. This output is in TRI-STATE mode when CS is de-asserted. This pin is bi-directional.
11 SCLK I Serial clock (SPI interface): Serial data are shifted into and out of the device synchronous with this clock signal. SCLK transitions with CS de-asserted are ignored. SCLK must be stopped when not required to minimize digital crosstalk.
12 VDD P Digital power supply
13 VCM I Input from ADC to control main output CM
14 −OUT O Main negative output
15 +OUT O Main positive output
16 VCM_AUX I Input to control auxiliary output CM
(1) G = Ground, I = Input, O = Output, P = Power