ZHCSMM2C March   2022  – October 2023 LMH34400

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Electrical Characteristics: Logic Threshold and Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Clamping and Input Protection
      2. 6.3.2 ESD Protection
      3. 6.3.3 Single-Ended Output Stage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Ambient Light Cancellation Mode
      2. 6.4.2 Power-Down Mode (Multiplexer Mode)
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 LMH34400 Test Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 LMH34400 Signal Chain With Comparator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Layout Guidelines

Achieving desired performance with a high-frequency amplifier such as the LMH34400 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include:

  • Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the output pins can cause instability whereas parasitic capacitance on the input pin reduces the amplifier bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  • Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times greater than the amplifiers maximum power supplies. Place the smallest-value capacitors on the same side as the DUT. If possible, use low equivalent series impedance capacitors to further reduce the parasitic impedance. If space constraints force the larger value bypass capacitors to be placed on the opposite side of the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration provides is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Use larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency on the supply pins. Place these decoupling capacitors further from the device.