Table 4. SD Clock Frequency Selection

Table 5. HD Clock Frequency Selection

8.1.6.2.1 Output TOF Clock

The TOF pulse is derived from a counter chain, which receives either output clock (SD_CLK or HD_CLK) from a 2:1 MUX block, as shown in Figure 12. The TOF clock from the MUX can be selected by programming TOF_CLK (register 0Ch). To select SD_CLK as the TOF clock, set TOF_CLK = 0; otherwise, set TOF_CLK = 1 to select HD_CLK. The selected TOF clock frequency is determined by the SD_FREQ or HD_FREQ register setting.

The TOF output delay time (t_{D_TOF}) for any output format generated from a TOF clock of 27 MHz is specified in Electrical Characteristics. The TOF output delay time for 525i and 1080i/50 generated using 27 MHz and 74.25 MHz, respectively, are shown in Typical Characteristics. The TOF pulse width can be determined by:

8.1.6.2.2 Output Frame Timing

The TOF pulse is specified by programming TOF_CLK, TOF_PPL (register 0Bh-0Ch) and TOF_LPFM (register 0Dh-0Eh). These registers configure the 2:1 MUX and output pixel and line counters in the TOF Generation blocks shown in Figure 12. The output frame or TOF pulse rate is determined by:

Example:

If the output format is 625i, then:

8.1.6.2.2.1 HD Format TOF Generation Using a 27-MHz TOF Clock

Any HD format TOF pulse can be generated using either: Option 1) its native HD clock frequency, or Option 2) the 27 MHz SD clock frequency.

Using Option 1) for HD output formats can result in TOF output delay being offset by more than one TOF clock period, even after output initialization. This is because the very short period of the HD native clock yields little timing margin for the reset signals to propagate through the internal logic in Figure 12. For example, using a TOF clock of 148.5 MHz gives less than 6.7 ns (< 1 clock cycle) for all the logic to completely synchronize and ensure proper output initialization.

To ensure proper output initialization, Option 2) is recommended for HD output formats, especially 1080p at 50, 59.94, and 60 Hz. This is because the longer period of the 27 MHz clock provides ample timing margin for the internal logic to reset. The output parameters for programming the HD output formats using the 27 MHz clock are shown in Table 2.

To illustrate both TOF clock options, an example is given below for 1080p/59.94, which has a native pixel clock frequency of 148.5/1.001 MHz and frame rate of 60/1.001 Hz:

Option 1) 1080p/59.94 TOF generation using 148.35 MHz

Equation 4.  TOF rate = 148.5/1.001 MHz / (2200 x 1125) = 60/1.001 Hz

where

•  f_{TOF_CLK} = 148.35 MHz (TOF_CLK = 1, HD_FREQ = 3h)
•  TOF_PPL = 2200
•  TOF_LPFM = 1125

Option 2) 1080p/59.94 TOF generation using 27 MHz

Equation 5.  TOF rate = 27 MHz / 2002 x 225) = 60/1.001 Hz

where

•  f_{TOF_CLK} = 27 MHz (TOF_CLK = 0, SD_FREQ = 0)
•  TOF_PPL = 2002
•  TOF_LPFM = 225

As an example, Figure 13 shows a timing illustration for 1080p/59 TOF and clock outputs. Once the outputs are initialized, the SD clock and TOF pulse will have a fixed delay, and the SD clock and HD clock will have a fixed timing offset relative to each other. Therefore, the timing offset between the TOF pulse and HD clock, or t_TOF-HD, will also be fixed and can be determined by:

Equation 6.  t_TOF-HD = t_{D_TOF} + t_{D_SD} - t_{D_HD}

where

•  t_{D_TOF} = TOF Output Delay Time referenced to SD_CLK
•  t_{D_SD} = SD_CLK Output Delay Time
•  t_{D_HD} = HD_CLK Output Delay Time

Figure 13. Timing Illustration Showing 1080p/59.94 TOF and CLK Output Delays Using Option 2

8.1.6.2.3 Reference Frame Timing

The reference format frame timing is generated internally and used for resetting the internal counters for output initialization. The reference frame rate should be specified by programming the reference format total lines per frame to REF_LPFM (register 0Fh-10h) as well as the PLL 1 dividers. See Table 2 for programming the parameter values according to each reference format. The reference frame rate is determined by:

8.1.6.2.4 Input-Output Frame Rate Ratio

The input-output frame rate ratio is also used for resetting the internal counters for output initialization. The ratio is the Input Frame Rate / Output Frame Rate, in which the numerator and denominator values are reduced to lowest integer factors. The numerator value of this reduced ratio should be programmed to TOF_RST (register 09h-0Ah), and the denominator value is discarded.

Example:

If the input reference is 525i with a frame rate of 30/1.001 Hz and the output format is 625i with a frame rate of 25 Hz, then:

 Frame rate ratio = (30/1.001) / 25 = 1200 / 1001

Therefore, the numerator, 1200, should be programmed to TOF_RST.

8.1.6.2.5 Output Frame Line Offset

The output clock and TOF pulse can be aligned to any line of the reference frame by programming TOF_OFFSET (register 11h-12h) and subsequently programming the output initialization sequence. The line offset value should be directly programmed to TOF_OFFSET to delay or advance the outputs' alignment relative to the decoded reference frame timing (see Reference Frame Decoder).

The TOF_OFFSET value must be greater than zero but less than or equal to the programmed value for REF_LPFM (i.e. 0 < TOF_OFFSET ≤ REF_LPFM). If no line offset is required, then program TOF_OFFSET equal to REF_LPFM instead of zero (invalid value).

Example:

If an input reference with PAL timing comes from the LMH1981, the H and V pulses will be aligned to within ΔT_HV which occurs on line 313 of the reference. In this case, TOF_OFFSET can be set to 312d (138h) so the output frame will align to Line 1 of the PAL reference (start of frame) after the outputs are initialized. This example is illustrated in Figure 14.

Figure 14. PAL Reference and Output TOF Pulse (TOF_OFFSET = 312)

8.1.6.3.1 TOF Output Delay Considerations

Due to the following conditions, the TOF pulse may be delayed or offset by more than one TOF clock period (t_{D_TOF} > 1 pixel) even after output initialization:

1. The delay paths of the internal logic used to generate and align the TOF pulse is greater than one period of the TOF clock. This can occur for HD format TOF pulses generated using the 148 MHz native pixel clock. For HD format TOF generation, it is recommended to use the 27 MHz SD clock as the TOF clock instead of the native HD pixel clock as shown in Output Frame Timing.
2. The H sync and/or V sync input pulses have excessive jitter equal to or larger than half of a pixel period of the selected output clock. Input sync jitter less than 3 ns peak-to-peak is recommended.
3. PLL 1 is not completely phase locked or stable when the output initialization is performed. The VCXO clock phase error with respect to the H sync input should less than one period of the selected TOF clock.

8.1.6.3.2 Output Clock Initialization Without TOF

For applications that do not require the TOF pulse, it is still necessary to program all output format registers prior to the output initialization sequence. This is because the output initialization circuitry relies on the full and correct specification of the output format. If the TOF output is not needed, it can be put in Hi-Z mode by setting TOF_HIZ = 1 (register 08h).

8.1.7.1.1 Programming the Loss of Reference (LOR) Threshold

The reference detector's error threshold can be programmed to H_ERROR (register 00h), which determines the maximum number of missing H sync pulses before indicating an LOR. The LOR threshold will be the H_ERROR value multiplied by the PLL 1 reference divider value, as shown in Table 6.

If H_ERROR = 0, then the device will react after the first missing pulse. When the LOR threshold is exceeded, the NO_REF output will indicate LOR, and the device will default to either Free Run or Holdover operation for as long as the reference is lost. As the LOR threshold value is increased, the accuracy for counting the actual number of missing H pulses may diminish due to frequency drifting by PLL 1.

8.1.7.2.1 Programming the PLL Lock Threshold

PLL 1's lock detector threshold can be programmed to LOCK_CTRL (register 01h), which determines the maximum phase error between PLL 1's phase detector (PD) inputs before indicating an unlock or lock condition. The PD inputs are the reference signal (H sync input / reference divider) and the feedback signal (VCXO clock / feedback divider).

The lock detector will indicate loss of lock when the phase error between the PD inputs is greater than the lock threshold for three consecutive phase comparison periods. Conversely, it will indicate valid lock when the phase error is less than the lock threshold for three consecutive phase comparison periods.

A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the opposite effect.

8.1.7.2.2 PLL Lock Status Instability

It is possible for excessive jitter on the H input to indicate lock instability through the NO_LOCK output, even if the VCXO and output clocks are properly phase locked and no system-level errors are occurring (e.g. bit errors). To reduce the probability of false loss of lock indication or lock status instability, LOCK_CTRL can be increased to improve the lock detector’s ability to tolerate a larger amount of input phase jitter or phase error. This can help to ensure the NO_LOCK output and SD_LOCK bit are stable when the reference signal has large input jitter.

8.1.8.1.1 Loop Response Optimization Tips

The need to support various input reference formats will usually require a diverse range of PLL divider values, which can each yield a different loop response assuming all other PLL parameters are kept the same. Typically, it is desired to design and optimize the loop response across all supported input formats without modification to the loop filter circuit. This requires that the loop gain, K, be kept constant across all supported divider values because K affects both BW and DF equations. To keep a narrow range for K, the ratio (I_CP1 / feedback divider) should be kept relatively constant. This can be achieved by programming ICP1, so that I_CP1 is scaled with FB_DIV for each supported input format.

It is suggested to start designing the loop filter component values from the BW and DF equations with initial assumptions of FB_DIV = 1716 (NTSC) and I_CP1 = 250 µA (default setting). Once reasonable component values are achieved under these initial assumptions, it is necessary to check that K can be maintained over the expected range of FB_DIV by adjusting I_CP1. The usable current range of I_CP1 is limited to a practical minimum of 94 µA (ICP1 = 3d) to a maximum of 969 µA (ICP1 = 31d), which should provide adequate range to maintain a narrow range for K assuming the suggested initial values for FB_DIV and I_CP1 were followed. If a narrow range for K cannot be maintained within the usable range of I_CP1, then the loop filter design may need to be modified. Some trial-and-error and iterative calculations may be necessary to find an optimal loop filter.

In some loop filter designs, the calculated I_CP1 current that is required for a target K value may be near or below the practical minimum of the I_CP1 current range. In this scenario, it may also be possible to leverage the programmable reference and feedback dividers by scaling up the values in proportion (i.e. same reduced divider ratio). This would allow I_CP1 to be scaled up by the same proportion to be within the usable I_CP1 current range and maintain the same K value, since I_CP1 and FB_DIV would be scaled by the same factor. For example, by scaling the divider values by a factor of 5x, I_CP1 can also be scaled up by 5x such that its within the usable current range. This technique of scaling FB_DIV and I_CP1 assumes that the input format has an alternative set of compatible divider values as shown in Table 2.

8.1.8.1.2 Loop Filter Capacitors

It is suggested to use tantalum capacitors for C_S and C_P instead of ceramic capacitors in the PLL loop filter, which is a sensitive analog circuit. Ferroelectric ceramics, such as X7R, X5R, Y5V, Y5U, etc., exhibit piezoelectric effects that generate electrical noise in response to mechanical vibration and shock. This electrical noise can modulate the VCXO control voltage and consequently induce clock jitter at high amplitudes when the board and ceramic components are subjected to vibration or shock. Tantalum capacitors can be used to mitigate this effect.

8.2.1.1.1 Programming the PLL 1 Dividers

To genlock the outputs to the reference, it is necessary to phase lock the VCXO clock (PLL 1) to the H sync input signal by programming the PLL dividers. The PLL divider values for each supported input reference format are given in Table 2. The divider values can be determined by reducing the following ratio to its lowest integer factors:

Table 8 shows the selection table with compatible PLL 1 reference divider values to program REF_DIV_SEL (register 03h). The PLL 1 feedback divider value can be directly programmed to FB_DIV (register 04h-05h).

8.2.1.2.1 Procedure for Designing the PLL 1 Dividers

Some supported input formats in Table 2 have two sets of compatible divider values: reduced dividers and non-reduced dividers. See Examples 2A and 2B below. Because the loop response of PLL 1 is dependent on the feedback divider value, a lower loop bandwidth and phase comparison frequency can be achieved by programming the non-reduced divider set (see Loop Response).

Examples:

1) For 1080i/59.94 input reference, the dividers are:

• Reference divider = 5 (REF_DIV_SEL = 2h)
• Feedback divider = 4004 (FB_DIV = FA4h)

2A) For 1080i/50 input reference, the reduced dividers are:

• Reference divider = 1 (REF_DIV_SEL = 1h)
• Feedback divider = 960 (FB_DIV = 3C0h)

2B) For 1080i/50 input reference, the non-reduced (alternative) dividers are:

• Reference divider = 5 (REF_DIV_SEL = 2h)
• Feedback divider = 4800 (FB_DIV = 12C0h)